SRAM memory cell with tri-level local interconnect

Static information storage and retrieval – Systems using particular element – Semiconductive

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365180, 257903, 257401, G11C 1140

Patent

active

053943589

ABSTRACT:
A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor. In a complementary fashion, the "false" inter-level interconnect connects: the drain of the "false" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "true" pull-up transistor and the "true" pull-down transistor, and a diffusion region defining and connecting the drain of the "false" access transistor and the drain of the "false" pull-down transistor. These two five-way connections provide all the necessary local interconnections for the memory cell. The reduced number of inter-level local interconnects required provides for denser memory cell layouts.

REFERENCES:
patent: 4794561 (1988-12-01), Hsu
patent: 4890141 (1989-12-01), Tang et al.
patent: 5128731 (1992-07-01), Lien et al.
patent: 5166902 (1992-11-01), Silver
Tang, Thomas, Che-Chia Wei, Roger Haken, Thomas Holloway, Chang-Feng Wan, and Monte Douglas, "VLSI Local Interconnect Level Using Titanium Nitride" IEDM 1985, pp. 590-593.

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