SRAM leakage reduction circuit

Details SRAM leakage reduction circuit SRAM leakage reduction circuit

2010-02-12

2011-12-13

Nguyen, Tuan (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S154000, C365S210120

Reexamination Certificate

active

08077527

ABSTRACT:
A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of VDD−(1.5*Vth), or maintain 1.5*Vthacross the memory cells, where Vthis a threshold voltage of an SRAM memory cell transistor and VDDis a positive supply voltage. By tracking the Vthof the memory cell transistors in the SRAM array, the circuit reduces leakage current while maintaining data integrity. A threshold voltage reference circuit can include one or more memory cell transistors (in parallel), or a specially wired memory cell to track the memory cell transistor threshold voltage. The value of the virtual ground reference voltage can be based on a ratio of feedback chain elements in a multiplier circuit.

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