SRAM formation using shadow implantation

Details SRAM formation using shadow implantation SRAM formation using shadow implantation

2007-11-20

2007-11-20

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S164000, C438S302000, C438S531000, C438S525000, C438S589000, C438S944000, C438S176000, C257SE21345, C257SE21442

Reexamination Certificate

active

11130161

ABSTRACT:
A method of doping fins of a semiconductor device that includes a substrate includes forming multiple fin structures on the substrate, each of the fin structures including a cap formed on a fin. The method further includes performing a first tilt angle implant process to dope a first pair of the multiple fin structures with n-type impurities and performing a second tilt angle implant process to dope a second pair of the multiple fin structures with p-type impurities.

REFERENCES:
patent: 4996574 (1991-02-01), Shirasaki
patent: 6765303 (2004-07-01), Krivokapic
patent: 6787406 (2004-09-01), Hill et al.
patent: 6855588 (2005-02-01), Liao et al.
patent: 6872647 (2005-03-01), Yu et al.
patent: 6924561 (2005-08-01), Hill et al.
patent: 2003/0102518 (2003-06-01), Fried et al.
patent: 2004/0108545 (2004-06-01), Ando
patent: 2004/0119100 (2004-06-01), Nowak et al.
patent: 2004/0188705 (2004-09-01), Yeo et al.
patent: 2004/0227187 (2004-11-01), Cheng et al.
patent: 2005/0001273 (2005-01-01), Bryant et al.
patent: 2005/0077574 (2005-04-01), Mouli
patent: 2005/0128787 (2005-06-01), Mouli
patent: 2005/0186738 (2005-08-01), Hofmann et al.
patent: 2004-281845 (2004-10-01), None
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/638,334, filed Aug. 12, 2003, entitled: “Systems and Methods for Forming Dense N-Channel and P-Channel Fins Using Shadow Implantation,” 16 page specification, 18 sheets of drawings.
Co-pending U.S. Appl. No. 10/429,697, filed May 6, 2003, entitled: “FinFET-Based SRAM Cell,” 16 page specification, 12 sheets of drawings.
J. I. Bergman et al.: “RTD/CMOS Nanoelectric Circuits: Thin-Film InP-Based Resonant Tunneling Diodes Integrated with CMOS Circuits,” IEEE Electron Device Letters, vol. 20, No. 3, Mar. 1999, pp. 119-122.
A. Seabaugh et al.: “Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,” IEDM, Dec. 8, 1998, 4 pages.
Co-pending U.S. Appl. No. 10/887,083, filed Jul. 9, 2004, entitled “Systems and Methods for forming dense n-channel and p-channel fins using shadow implanting”.

Affiliated with

Also associated with

Rating

SRAM formation using shadow implantation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM formation using shadow implantation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM formation using shadow implantation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3836792