SRAM device with enhanced read/write operations

Details SRAM device with enhanced read/write operations SRAM device with enhanced read/write operations

2007-10-25

2009-11-03

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

For complementary information

C365S156000

Reexamination Certificate

active

07613054

ABSTRACT:
An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device.

REFERENCES:
patent: 5831897 (1998-11-01), Hodges

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