SRAM device with a low operation voltage

Details SRAM device with a low operation voltage SRAM device with a low operation voltage

2006-09-27

2008-12-23

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189011, C365S185140

Reexamination Certificate

active

07468902

ABSTRACT:
An SRAM cell includes: a first PMOS transistor having a source coupled to a supply voltage; a second PMOS transistor having a source coupled to the supply voltage, a drain coupled to a gate of the first PMOS transistor, and a gate coupled to a drain of the first PMOS transistor; a first write switch module coupled between the first PMOS transistor and a complementary supply voltage; a second write switch module coupled between the second PMOS transistor and the complementary supply voltage; and a read switch module coupled between the gate of the first PMOS transistor and a read bit line, wherein the first write switch module, the second write switch module, and the read switch module are controlled separately to write or read a logic value to or from one or more storage nodes at the drains of the first and second PMOS transistors.

REFERENCES:
patent: 7239558 (2007-07-01), Poplevine et al.
patent: 2003/0107913 (2003-06-01), Nii
patent: 2008/0013383 (2008-01-01), Venkatraman et al.

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