SRAM device and a method of operating the same to reduce...

Details SRAM device and a method of operating the same to reduce... SRAM device and a method of operating the same to reduce...

2007-12-11

2007-12-11

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S226000, C365S227000, C365S228000, C365S229000, C365S154000, C365S156000

Reexamination Certificate

active

10732970

ABSTRACT:
An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) a sleep mode voltage controller configured to provide both an array high supply voltage VADDthat is lower than a high operating voltage VDDand an array low supply voltage VASSthat is higher than a low operating voltage VSSto the SRAM array during a sleep mode.

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Theodore W. Houston, et al. “Bit Line Control for Low Power in Standby” U.S. Appl. No. 10/337,069, filed Jan. 6, 2003, TI-34949.
Theodore W. Houston, et al. “SRAM with Temperature-Dependent Voltage Control in Sleep Mode” U.S. Appl. No. 10/745,429, filed Dec. 22, 2003, TI-36138.
Xiaowei Deng, et al., “A Low Leakage SRAM Scheme” U.S. Appl. No. 10/349,277, filed Jan. 22, 2003, TI-34973.

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