SRAM device

Details SRAM device SRAM device

2002-01-14

2003-04-01

Lam, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S203000, C365S156000

Reexamination Certificate

active

06542401

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an SRAM device, and more particularly to stabilizing the operation thereof.
In a conventional 6-transistor SRAM device, an inter line coupling occurs between a pair of bit lines BL
1
and /BL
1
, thereby causing coupling noise. In order to suppress the coupling noise, there is a technique of shielding bit lines by, for example, providing a separate ground line Vss between the pair of bit lines BL
1
and /BL
1
in the same wiring layer.
FIG. 10
illustrates a memory cell
100
of an SRAM device produced by using this technique.
FIG. 11
is a cross-sectional view schematically illustrating wiring layers and connection holes in an area above three memory cells
100
.
FIG. 11
is a cross-sectional view taken along line XI—XI shown in
FIG. 10
, schematically illustrating all the connection holes and the lines connected thereto being projected onto a plane.
As illustrated in
FIG. 10
, a total of three lines, including two bit lines (BL
1
and /BL
1
) and a ground line Vss, are connected to the memory cell
100
. As illustrated in
FIG. 11
, the lines are arranged at substantially the minimum pitch both in the bit line width direction and in the connection hole depth direction.
In an SRAM device including the memory cell
100
illustrated in FIG.
10
and
FIG. 11
, the two bit lines BL
1
and /BL
1
are completely shielded from each other by the ground line Vss provided therebetween, thereby suppressing the coupling noise in the bit line pair. However, the distance between each of the two bit lines BL
1
and /BL
1
and the ground line Vss is short, thereby increasing the line capacitance. Particularly, the line capacitance further increases as the interval between lines decreases along with the miniaturization of memory cells. The small interval between lines increases the chance of the two bit lines BL
1
and /BL
1
being short-circuited with the ground line Vss due to a process dust defect. If the two bit lines BL
1
and /BL
1
are short-circuited with the ground line Vss, a short-circuit leak current flows via a precharge circuit while the two bit lines BL
1
and /BL
1
are being precharged to the power supply voltage. This leak current remains even if the two bit lines BL
1
and /BL
1
are replaced by a redundant cell.
As illustrated in
FIG. 11
, no line is provided between the memory cell
100
and an adjacent bit line (/BL
0
, BL
2
). Therefore, coupling noise still occurs between /BL
0
and BL
1
and between /BL
1
and BL
2
.
The problem of coupling noise can be solved by providing a shielding ground line or a shielding power supply line between the two bit lines (BL
1
and /BL
1
) of the memory cell
100
and the respective adjacent bit lines (/BL
0
and BL
2
). Then, however, the interval between a bit line and the shielding ground line or the shielding power supply line is very small, thereby further increasing the line capacitance. This increases the charging/discharging time of the pair of bit lines (BL
1
and /BL
1
), thereby presenting a problem that there will be an increased amount of time before a potential change of 100 mV, for example, occurs, i.e., an increased delay time until the timing at which a read sense amplifier is turned ON.
In a write operation, the voltage applied to each of the two bit lines (BL
1
and /BL
1
) dynamically changes from the power supply voltage to the ground level. Then, quite substantial coupling noise occurs between the adjacent bit lines /BL
0
and BL
1
and between the adjacent bit lines /BL
1
and BL
2
. This substantially changes the voltages being applied to the adjacent bit lines /BL
0
and BL
2
. Therefore, the information stored in a memory cell adjacent to the memory cell
100
may be destroyed.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve the problems described above, and has an object to provide an SRAM device capable of performing a stable operation.
An SRAM device of the present invention is an SRAM device, including: a plurality of bit line pairs that are arranged substantially parallel to one another and connected to different memory cells, respectively; selection means for selecting one bit line pair from among the plurality of bit line pairs; and potential holding means for holding a precharge potential of bit lines that are respectively on opposite sides of the one bit line pair with the one bit line pair being selected, wherein an interval between two adjacent bit line pairs is smaller than an interval between two bit lines of the same bit line pair.
By holding the precharge potential of bit line pairs that are adjacent to, and respectively on opposite sides of, a selected bit line pair, the bit lines that are adjacent to, and respectively on opposite sides of, the selected bit line pair can behave as shield lines for the selected bit line pair. Therefore, it is possible to improve the shield effect against the coupling noise between the selected bit line pair and each of the bit lines that are adjacent to, and respectively on opposite sides of, the selected bit line pair, without providing any additional elements or lines. Moreover, the precharge operation is continued for the adjacent bit line pairs, and they behave as if they were power supply lines. Therefore, it is no longer necessary to take into consideration the influence of the coupling between two adjacent bit line pairs. Thus, the interval between two adjacent bit line pairs can be reduced, whereby it is possible to increase the interval between two bit lines of the same pair. Therefore, with the SRAM device of the present invention, it is possible to reduce the capacitance occurring between two bit lines of the same pair. Thus, it is possible to reduce the coupling noise without separately providing a special-purpose shield line between the bit lines of the same pair.
Since the interval between the bit lines of the same pair is large and no special-purpose shield line is provided between the two bit lines of the same pair, a short circuit will not occur between each bit line in one bit line pair and a shield line. Therefore, a short-circuit leak current is prevented from flowing via a precharge circuit while all of the bit lines are precharged to the power supply voltage.
Since the interval between two adjacent bit line pairs is small, it is possible that a short-circuit occurs between two adjacent bit line pairs. However, since all the bit lines are at an equal potential when the bit lines are precharged to the power supply voltage, a short-circuit leak current does not occur due to the short-circuit.
The potential holding means may hold a precharge potential of all of the plurality of bit line pairs excluding the selected bit line pair.
The potential holding means may hold a precharge potential of odd-numbered bit line pairs, counting from the selected bit line pair, and may not hold a precharge potential of even-numbered bit line pairs, counting from the selected bit line pair.
The number of bit line pairs whose precharge potential is held by the potential holding means may be greater than the number of bit line pairs whose precharge potential is not held by the potential holding means.
The potential holding means may hold a precharge potential only in a write operation.
It is preferred that the interval between two adjacent bit line pairs is smaller, and the interval between two bit lines of the same bit line pair is larger, than a thickness of each bit line of the plurality of bit line pairs.
In this way, it is possible to reduce the line capacitance in each bit line pair.
It is preferred that the SRAM device further includes a plurality of wiring layers, wherein one of the plurality of wiring layers in which the bit lines are provided includes no line other than the bit lines in regions above the memory cells.
By providing a special-purpose wiring layer for bit lines, it is possible to ensure a large line interval between a bit line and each of two wiring layers that are respectively above and below the bit line.
It is preferred that: the plurality

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