SRAM-compatible memory and method of driving the same

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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C711S105000

Reexamination Certificate

active

07085882

ABSTRACT:
Disclosed herein are an SRAM-compatible memory and method of driving the SRAM-compatible memory. The SRAM-compatible memory has memory banks, a parity generator and a parity bank. The memory banks each store corresponding one of input data in its DRAM cells specified by an input address. The memory banks perform write operations independently such that when a refresh operation or a write operation for a previous frame is being performed with respect to DRAM cells of a certain memory bank, the write operation of the input data is independently performed with respect to the respective memory banks except for the certain memory bank. The parity generator generates a input parity determined based on the input data and a certain preset parity value. The parity bank stores the input parity.

REFERENCES:
patent: 5999474 (1999-12-01), Leung et al.
patent: 6757784 (2004-06-01), Lu et al.
patent: 2002/0016942 (2002-02-01), MacLaren et al.
patent: 2003/0106010 (2003-06-01), Fujioka et al.
patent: 2003/0185078 (2003-10-01), Tsukude
patent: 10-0190248 (1999-01-01), None
patent: 2002-0025272 (2002-04-01), None

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