SRAM cells with two P-well structure

Details SRAM cells with two P-well structure SRAM cells with two P-well structure

2000-05-05

2004-01-13

Nadav, Ori (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S393000, C257S904000

Reexamination Certificate

active

06677649

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor integrated circuit devices and, more particularly, to layout schemes of static random access memory (SRAM) cells. The invention also relates to semiconductor memory devices using such cells.
One-port SRAM cells with complementary metal oxide semiconductor (CMOS) configurations are typically designed so that each cell consists essentially of six separate transistors. An exemplary layout of such cells has been disclosed, for example, in JP-A-10-178110 (laid open on Jun. 30, 1998).
In the previously known SRAM cell layout, a semiconductive well region of P type conductivity with inverters formed therein is subdivided into two subregions, which are disposed on the opposite sides of an. N-type well region while permitting a well boundary line to extend in a direction parallel to the bit lines.
The quest for higher integration and ultra-fine patterning techniques in modern memory devices requires an optical exposure apparatus or equipment to decrease the wave length of the beams used therein. To this end, the equipment is designed to employ exposure beams of shorter wavelengths, which have advanced from G line to I line, and then further to excimer lasers. Unfortunately, the requirements for micro-patterning architectures have grown more rapidly than technological advance in the trend of shortening wavelengths in such equipment. In recent years, it has been strictly required that micropatterning be done with the minimum device-feature length that shrinks to less than or equal to the wavelength of the exposure beam used. This minimum feature length shrinkage would result in a layout of IC components—particularly, memory cells—becoming more complicated in planar shape, which necessitates the use of irregular polygonal layout patterns including key-shaped components, in order to achieve the intended configuration of an on-chip circuitry with enhanced accuracy. This makes it impossible, or at least very difficult, to microfabricate ultrafine layout patterns while disadvantageously serving as the cause of the destruction of the symmetry of memory cells.
Regrettably, the prior art approach is associated with a need to curve or bend a diffusion layer into a complicated key-like shape for the purpose of making electrical contact with a substrate of the P-type well region. Thus, the prior art suffers from the problem of the degradation of the symmetrization of the cell layout pattern, making the successful achievement of microfabrication architectures for higher integration densities difficult.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a semiconductor device is provided which comprises a first inverter including a first N-channel metal oxide semiconductor MOS transistor, and a first channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being connected to an output terminal of the first inverter and with an output terminal being connected to an input terminal of said first inverter, a third N-channel MOS transistor having a source connected to the output terminal of said first inverter, a drain connected to a first bit line, and also a gate connected to a word line, and a fourth N-channel MOS transistor having a source connected to the output terminal of said second inverter, a drain connected to a second bit line, and a gate connected to a word line, wherein the first and third N-channel MOS transistors are formed in a first P-type well region, wherein the diffusion layer has no curved or bent portions, while letting the direction of the layout be parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein, and wherein said second and fourth N-channel MOS transistors are formed in the second P-type well region, whose diffusion layer has no bent portions, while letting the layout direction be parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein.
The diffusion layer is arranged to have its outer shape, which mainly consists of straight line segments including the longest straight line portion, which lies parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein, and simultaneously in the case of defining a straight line acting as the center line extending parallel to such a boundary, the longest line portion is in linear symmetry with said center line; the second and fourth N-channel MOS transistors are formed in the second P-well region, whose diffusion layer is mainly arranged by straight line segments including its longest straight line portion that is parallel to the boundary with respect to the first N-well region with the first and second P-channel MOS transistors formed therein while allowing, when defining a straight line for use as the center line extending parallel to such a boundary, the line portion to be linearly symmetrical to the center line. At this time, in the case of employing the linear symmetrization scheme, complete linear symmetry will not always be required. Alternatively, slight nonsymmetry may also be permissible on a case-by-case basis. This nonsymmetry results from modifying the diffusion layer to have a shape in which its portions on the right and left sides of the center line are substantially the same in area as each other, by way of example.
In accordance with another aspect of this invention, a first polycrystalline silicon lead layer for use as the gate of said third N-channel MOS transistor and a second polycrystalline silicon lead layer for use as the gate of said first P-channel MOS transistor, and also as the gate of said first N-channel MOS transistor, are disposed in parallel to each other, wherein a third polycrystalline silicon lead layer for use as the gate of said fourth N-channel MOS transistor, and a fourth polycrystal-line silicon lead layer for use as the gate of said second N-channel MOS transistor, and also as the gate of said second P-channel MOS transistor are disposed in parallel to each other, and wherein the first and third polycrystalline silicon lead layers are connected via a contact to a second layer which serves as a metal lead layer constituting the word lines.
In accordance with another aspect of the invention, the input terminal of said first inverter and the output terminal of said second inverter may be electrically connected together at a contact, whereas the input terminal of said second inverter and the output terminal of said first inverter are electrically connected together at a contact.
In accordance with yet another aspect of the invention, a power supply line connected to the first and second bit lines, the sources of said first and second P-channel MOS transistors, and a ground line connected to the sources of said first and second N-channel MOS transistors may be formed of a third layer serving as a metal lead layer lying parallel to a diffusion layer.
In accordance with a still another aspect of the invention, the first bit line formed of said third layer serving as a metal lead layer may be arranged so that it is between a power supply line formed of said third layer serving as a lead layer and a ground line as connected to the source of said first N-channel MOS transistor formed of said third layer serving as a metal lead layer whereas the second bit line formed of said third layer serving as a metal lead layer is between a power supply line formed of said third layer serving as a metal lead layer and a ground line as connected to the source of said second N-channel MOS transistor formed of said third layer serving as a metal lead layer.
In accordance with another aspect of the invention, the first and second bit lines and a power supply line connected to the sources of said first and second P-channel MOS transistors may be formed of a second layer serving as a metal lead layer, wh

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