SRAM cell with thin film transistor using two polysilicon layers

Details SRAM cell with thin film transistor using two polysilicon layers SRAM cell with thin film transistor using two polysilicon layers

1997-07-24

2000-08-22

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 69, 365156, H01L 27108

Patent

active

061076422

ABSTRACT:
A TFT formed on a semiconductor substrate of a first conductivity type, includes a first doped portion of a polysilicon layer over FOX regions and a first insulating layer. A buried contact extends through the first portion of a polysilicon layer and the first insulating layer to the surface of the substrate adjacent to a FOX region. A second doped portion of the polysilicon layer overlies the first portion and forms a buried contact between the second portion and the substrate. The polysilicon layer forms a gate electrode and a conductor from the buried contact. Doped source/drain regions in the substrate are juxtaposed with the gate electrode. An interelectrode dielectric layer over the gate electrode and the conductor has a gate opening therethrough down to the substrate. A gate oxide layer is formed on the surface of the substrate at the gate opening. A semiconductor film extends over the interelectrode dielectric layer and over the surface of the substrate through the gate opening. A doped channel region is formed between source/drain regions in the semiconductor film above the gate opening, and above the gate opening of a TFT, with the doped region therebelow comprising the gate of the TFT.

REFERENCES:
patent: 4980732 (1990-12-01), Okazawa
patent: 5151374 (1992-09-01), Wu
patent: 5491654 (1996-02-01), Azuma
patent: 5506436 (1996-04-01), Hayashi et al.
patent: 5640342 (1997-06-01), Gonzales

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