SRAM cell with single-ended and differential read/write ports

Details SRAM cell with single-ended and differential read/write ports SRAM cell with single-ended and differential read/write ports

2002-09-13

2004-05-18

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000, C365S156000

Reexamination Certificate

active

06738306

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to SRAMs (static random access memories) and, more particularly, to a SRAM (static random access memory) cell having multiple ports.
BACKGROUND
A SRAM (static random access memory) is known to one of ordinary skill in the art of electronics for storing data without need for periodic refresh of data. A SRAM is comprised of an array of SRAM cells. For some applications, data of the SRAM is simultaneously shared by a plurality of memory accessing devices. For such applications, the SRAM cell of the SRAM array is a multiport SRAM cell for providing access to the data of the SRAM cell by a plurality of memory accessing devices.
FIG. 1
shows an example multiport SRAM cell
100
of the prior art as described in U.S. Pat. No. 6,097,664 to Nguyen et al. The SRAM cell
100
of
FIG. 1
includes a bistable loop of a first inverter
102
and a second inverter
104
. The first inverter
102
is comprised of a first PMOSFET (P-channel metal oxide semiconductor field effect transistor)
106
and a first NMOSFET (N-channel metal oxide semiconductor field effect transistor)
108
coupled between a positive power supply V
CC
119
and the ground node
121
. The second inverter
104
is comprised of a second PMOSFET
110
and a second NMOSFET
112
coupled between the positive power supply V
CC
119
and the ground node
121
. The input of the first inverter
102
is coupled to the output of the second inverter
104
at a first bistable node
114
, and the input of the second inverter
104
is coupled to the output of the first inverter
102
at a second bistable node
116
. The first and second bistable nodes
114
and
116
store the data of the SRAM cell
100
, as known to one of ordinary skill in the art of electronics.
In addition, the SRAM cell
100
includes a third inverter
118
, which is a read driver inverter, having an input coupled to the second bistable node
116
. The third inverter
118
is comprised of a third PMOSFET
120
and a third NMOSFET
122
coupled between the positive power supply V
CC
119
and the ground node
121
. The output of the third inverter
1
18
is coupled to inputs of a first pass gate
124
and a second pass gate
126
. First read access control signals RA
1
and RA
1
* (the complement of RA
1
) are provided by a first memory accessing device to the first pass gate
124
for reading the data at the second bistable node
116
, via the read driver inverter
118
, of the SRAM cell
100
as output signal RD
1
. Second read access control signals RA
2
and RA
2
* (the complement of RA
2
) are provided by a second memory accessing device to the second pass gate
126
for reading the data at the second bistable node
116
, via the read driver inverter
118
, of the SRAM cell
100
as output signal RD
2
. The first and second pass gates
124
and
126
are comprised of a pair of a PMOSFET and an NMOSFET, and such implementation of pass gates is known to one of ordinary skill in the art of electronics.
Furthermore, the SRAM cell
100
includes a third pass gate
128
coupled to the first bistable node
114
. One of the first or second memory accessing devices provides first write access control signals WA
1
and WA
1
* (the complement of WA
1
) to the third pass gate
128
for writing input data WD
1
to the first bistable node
114
of the SRAM cell
100
. The third pass gate
128
is comprised of a pair of a PMOSFET and an NMOSFET, and such implementation of a pass gate is known to one of ordinary skill in the art of electronics.
Additionally, a pass transistor
130
is coupled to the first bistable node
114
. A memory accessing device provides access control signal WA
2
to the pass transistor
130
for either reading data R/WD
2
from the first bistable node
114
of the SRAM cell
100
or for writing data R/WD
2
to the SRAM cell
100
. For example, the memory accessing device coupled to the pass transistor
130
includes portions
132
and
136
of a serial boundary scan subsystem. The portion
136
of the serial boundary scan subsystem functions to serially provide data R/WD
2
to be written into the SRAM cell
100
or alternatively to serially receive data R/WD
2
read from the SRAM cell
100
, from or into a respective location
138
of the portion
136
of the serial boundary scan subsystem. The portion
132
of the serial boundary scan subsystem functions to serially provide the access control signal WA
2
from the respective location
134
of the portion
132
of the serial boundary scan subsystem.
The portions
132
and
136
of the serial boundary scan subsystem are used for writing and reading initial configuration data to be stored by the SRAM cell
100
, as described in U.S. Pat. No. 6,097,664 to Nguyen et al. The portions
132
and
136
of the serial boundary scan subsystem are typically already present within a memory system such that such initial configuration data may be stored into the SRAM cell
100
without significant added circuitry of the memory system. In addition, by using a single pass transistor
130
(instead of a two-MOSFET pass gate), the metal lines from the portions
132
and
136
of the serial boundary scan subsystem for writing and verifying the initial configuration data within the SRAM cell
100
are advantageously minimized.
In the SRAM cell
100
, the first PMOSFET
106
and the first NMOSFET
108
of the first inverter
102
are sized to be larger than the second PMOSFET
110
and the second NMOSFET
112
, respectively, of the second inverter
104
. Thus, the W/L (i.e., the width over length) ratio of the first PMOSFET
106
is larger than the W/L (i.e., the width over length) ratio of the second PMOSFET
110
, and the W/L (i.e., the width over length) ratio of the first NMOSFET
108
is larger than the W/L (i.e., the width over length) ratio of the second NMOSFET
112
.
In that case, the MOSFETs
106
and
108
of the first inverter
102
have higher transconductance, G
M
, than that of the MOSFETs
110
and
112
of the second inverter
104
. As a result, for writing data into the SRAM cell
100
, the write data via the third pass gate
128
or via the pass transistor
130
is applied on the input (i.e., the first bistable node
114
) of the first inverter
102
rather than on the input of the second inverter
104
. The output
116
of the first inverter
102
with the MOSFETs
106
and
108
having higher transconductance over-powers the output
114
of the second inverter
104
. Thus, the write data for the write operation is applied on the input (i.e., the first bistable node
114
) of the first inverter
102
for proper write operation when the MOSFETs
106
and
108
of the first inverter
102
have higher transconductance than that of the MOSFETs
110
and
112
of the second inverter
104
.
Because the MOSFETs of the first and second inverters
102
and
104
are differently sized, the multiports comprising the first, second, and third pass gates
124
,
126
,
128
and the pass transistor
130
are each single-ended, accessing only one of the first or second bistable nodes
114
and
116
. The ports comprising the first and second pass gates
124
and
126
access the single second bistable node
116
via the read driver inverter
118
for reading data from the SRAM cell
100
. The ports comprising the third pass gate
128
and the pass transistor
130
access the single first bistable node
114
for writing data to the SRAM cell
100
. The port comprising the pass transistor
130
also accesses the single first bistable node
114
for reading data from the SRAM cell
100
.
A disadvantage of the SRAM cell
100
of
FIG. 1
is that each of the multiports comprising the first, second, and third pass gates
124
,
126
,
128
does not have the dual functionality of both reading and writing to the SRAM cell
100
. The ports of the SRAM cell
100
comprising the first and second pass gates
124
and
126
are read only, and the port comprising the third pass transistor
128
is write only. In addition, because the ports of the SRAM cell
100
comprising the first,

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