SRAM cell with capacitor

Details SRAM cell with capacitor SRAM cell with capacitor

1993-12-03

1996-07-30

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257374, 257397, 257513, 257752, 257903, H01L 27108, H01L 2711

Patent

active

055414273

ABSTRACT:
A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch. A six device SRAM cell comprises a deep isolation trench formed in the substrate; a first latch including two transistors formed of p-type material on a first side of the trench; a second latch including two transistors formed of n-type material on a second side of the trench opposite the first side of the trench, and connection means for electrically cross wiring the transistors of the first latch to the transistors of the second latch. In forming the latch a self-aligned process for separately forming contacts to diffusion regions and gate stacks on the semiconductor substrate is used.

REFERENCES:
patent: 4409722 (1982-10-01), Dockerty et al.
patent: 4653025 (1987-03-01), Minato et al.
patent: 4740479 (1988-04-01), Neppl et al.
patent: 4785341 (1988-11-01), Ning et al.
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4944682 (1990-07-01), Cronin et al.
patent: 4966870 (1990-10-01), Barber et al.
patent: 5045916 (1991-09-01), Vor et al.
patent: 5072286 (1991-12-01), Minami et al.
patent: 5145799 (1992-09-01), Rodder
patent: 5173450 (1992-12-01), Wei
patent: 5187638 (1993-02-01), Sandhu et al.
patent: 5227649 (1993-07-01), Chapman
patent: 5243203 (1993-09-01), Hayden et al.
patent: 5246876 (1993-09-01), Manning
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5334862 (1994-08-01), Manning et al.
Debrosse et al. "Contact Process Providing Layout Advantages In A Static Random-Access Memory Cell:IBM TDB" vol. 32 No. 9A, Feb. 1990, pp. 434-436.
Dittrich, M. "Vertical Drive Device Polysilicon Load Static Random-Access Memory Cell:IBM TDB" vol. 31, No. 7, Dec. 1988, pp. 230-234.
Chesebro, D. et al., "Simplified Local Interconnection Technique For Sram and Logic Semiconductor Structures" IBM TDB vol. 34, No. 1, Jun. 1991 pp. 328-330.
F. White et al., "Damascene Stud Local Interconnect In CMOS Technology" IEDM 1992 pp. 301-304.
D. Kenney et al., "A Buried-Plate Trench Cell for n 64-Mb DRAM" 1992 Symposium on VLSI Technology Digest of Technical Papers, 1992 IEEE pp. 14-15.
R. D. J. Verhaar, et al. "A 25 .mu.m.sup.2 Bulk Full CMOS Sram Cell Technology With Fully Overlapping Contacts", IEDM 1990, IEEE pp. 473-476.
M. Helm et al., "A Low Cost, Microprocessor Compatible, 18.4 .mu.m.sup.2, 6-T Bulk Cell Technology for High Speed SRAMS" VLSI 93' 2 pages.

Affiliated with

Also associated with

Rating

SRAM cell with capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM cell with capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM cell with capacitor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1661020