SRAM cell with bootstrapped power line

Details SRAM cell with bootstrapped power line SRAM cell with bootstrapped power line

2003-05-30

2004-09-14

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S154000, C365S228000

Reexamination Certificate

active

06791886

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic data storage devices, and more particularly to a system and method for bootstrapping a power line in a data storage cell to provide a power boost in a memory cell.
2. Description of the Related Art
Static memory storage devices are subjected to more constraints at low voltages. With the portability of active or switching memory devices, power becomes a greater concern with higher performance requirements since power levels are generally lower and limited by portable power storage devices. These difficulties make the design of storage cells for portable applications more challenging.
For example, designing complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells for high performance becomes particularly challenging at low power supply voltages, which are typically employed for portable applications. The data stored in a cell becomes increasingly vulnerable to a read upset at these low power voltages. In addition, the scalability of the supply voltage is also limited for conventional CMOS SRAM cells, due to dopant fluctuations in small-geometry cell transistors.
SUMMARY OF THE INVENTION
A memory cell includes at least one active device, for example a PFET, for selectively connecting a supply voltage node to a power line preferably during a standby state. The power line couples capacitive elements through the at least one active device to the supply voltage node to maintain a boosted voltage.
In another embodiment, a memory cell includes a storage node, and a first device for selectively connecting a supply voltage node to a power line through the storage node. The power line couples capacitive elements to the supply voltage node to hold a state while accessing the storage node.
In yet another embodiment, a random access memory cell includes a storage node which stores charge in accordance with a state of a bit line and an activation of a wordline, and a CMOS device having gates of an NFET and a PFET connected to the storage node. A power line provides capacitive coupling to the wordline such that upon activation of the wordline the PFET conducts to augment a state of a supply voltage to boost the state of the storage node.
Other embodiments may include the following features or elements. The wordline may be formed on a first layer of a semiconductor device and the power line may be formed on an adjacent layer. The wordline may be separated by a predetermined distance from the power line to provide the capacitive coupling therebetween, and the wordline is preferably separated from the power line by a dielectric material selected to provide an appropriate capacitive coupling therebetween.
The capacitive coupling may include capacitive components, for example, capacitance between the wordline and the power line, and/or capacitance between the power line and ground. The capacitive coupling preferably provides a voltage of greater than Vdd when maintaining data on the storage node. The capacitive coupling may include a voltage equal to Vdd(C
c
/(C
c
+C
M
)), where C
c
is the capacitance between the wordline and the power line, and C
M
is the capacitance to ground of the power line.
These and other objects, features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 6388936 (2002-05-01), Itoh et al.
patent: 6515893 (2003-02-01), Bhavnagarwala
patent: 6529400 (2003-03-01), Bhavnagarwala et al.
patent: 6556471 (2003-04-01), Chappell et al.
patent: 2003/0043618 (2003-03-01), Nakura et al.

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