SRAM cell design with high resistor CMOS gate structure for...

Details SRAM cell design with high resistor CMOS gate structure for... SRAM cell design with high resistor CMOS gate structure for...

2007-12-11

2007-12-11

Pham, Ly Duy (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S063000, C365S072000, C365S188000, C257S388000, C257S413000, C257S536000, C257S538000, C257SE27098, C257SE29156, C257SE29161, C438S210000, C438S649000, C438S682000

Reexamination Certificate

active

11287449

ABSTRACT:
A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

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patent: 2004/0136128 (2004-07-01), Kato
patent: 2005/0248977 (2005-11-01), Liaw

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