SRAM cell design for soft error rate immunity

Details SRAM cell design for soft error rate immunity SRAM cell design for soft error rate immunity

2005-12-06

2005-12-06

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S204000, C257S297000, C257S379000, C257S393000, C257S532000

Reexamination Certificate

active

06972450

ABSTRACT:
A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.

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