Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate
2007-04-26
2008-08-05
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Including specified plural element logic arrangement
C365S154000, C365S189120
Reexamination Certificate
active
07408815
ABSTRACT:
First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.
REFERENCES:
patent: 6222757 (2001-04-01), Rau et al.
patent: 7099189 (2006-08-01), Plants
Actel Corporation
Hoang Huan
Lewis and Roca LLP
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