SRAM cell comprising a reference transistor for neutralizing...

Details SRAM cell comprising a reference transistor for neutralizing... SRAM cell comprising a reference transistor for neutralizing...

2007-10-09

2007-10-09

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

Reexamination Certificate

active

11197737

ABSTRACT:
A memory cell comprises a first inverter (IA) and a second inverter (IB) coupled upside down to each other between a first node (A) and a second node (B), and a first access transistor (TA) having a drain coupled to the first node (A), a gate coupled to a word line (WL) and a source coupled to a bit line (BLREAD). The memory cell also comprises a reference transistor (TC) having a drain coupled to the first node (A) and a source coupled to a reference line (BLREF), a cut-off potential (GND) being applied to a gate of the reference transistor (TC). Moreover, an SRAM cell comprising a reference transistor for neutralizing leakage current and associated read and write method is described.

REFERENCES:
patent: 4956815 (1990-09-01), Houston
patent: 6198656 (2001-03-01), Zhang
patent: 6262911 (2001-07-01), Braceras et al.
patent: 6707708 (2004-03-01), Alvandpour et al.
patent: 2004/0047176 (2004-03-01), Alvandpour et al.
patent: WO 2004/049348 (2004-06-01), None

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