SRAM cell and SRAM device

Details SRAM cell and SRAM device SRAM cell and SRAM device

2007-12-20

2011-10-18

Lam, David (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S063000, C365S177000

Reexamination Certificate

active

08040717

ABSTRACT:
A static random access memory (SRAM) cell includes a first to a fourth semiconductor thin plate that are provided on a substrate and are arranged parallel to each other. On respective semiconductor thin plates, there is formed a first four-terminal double-gate field effect transistor (FET) with a first conductivity type, a second and a third four-terminal double-gate FET which are connected in series with each other and have a second conductivity type, a fourth and a fifth four-terminal double-gate FET which are connected in series with each other and have the second conductivity type, and a sixth four-terminal double-gate FET with the first conductivity type. The third and the fourth four-terminal double-gate FETs form select transistors, and the first, second, fifth and sixth four-terminal double-gate FETs form a complementary metal-oxide-semiconductor (CMOS) inverter.

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