SRAM cell

Details SRAM cell SRAM cell

2005-07-19

2005-07-19

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257SE27098

Reexamination Certificate

active

06919647

ABSTRACT:
A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.

REFERENCES:
patent: 3755012 (1973-08-01), George et al.
patent: 4300064 (1981-11-01), Eden
patent: 4468574 (1984-08-01), Engeler et al.
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5349228 (1994-09-01), Neudeck et al.
patent: 5384731 (1995-01-01), Kuriyama et al.
patent: 5436506 (1995-07-01), Kim et al.
patent: 5677550 (1997-10-01), Lee
patent: 5773331 (1998-06-01), Solomon et al.
patent: 6064589 (2000-05-01), Walker
patent: 6072354 (2000-06-01), Tachibana et al.
patent: 6097221 (2000-08-01), Sako
patent: 6104068 (2000-08-01), Forbes
patent: 6188243 (2001-02-01), Liu et al.
patent: 6365465 (2002-04-01), Chan et al.
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6404237 (2002-06-01), Mathew et al.
patent: 6420905 (2002-07-01), Davis et al.
patent: 6433609 (2002-08-01), Voldman
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6506638 (2003-01-01), Yu
patent: 6518127 (2003-02-01), Hshieh et al.
patent: 6580137 (2003-06-01), Parke
patent: 6818487 (2004-11-01), Hsu et al.
patent: 2001/0022521 (2001-09-01), Sasaki et al.
patent: 2002/0047727 (2002-04-01), Mizuno
patent: 2002/0081808 (2002-06-01), Forbes
patent: 2002/0084803 (2002-07-01), Mathew et al.
patent: 2002/0093053 (2002-07-01), Chan et al.
patent: 2002/0105039 (2002-08-01), Hanafi et al.
patent: 2002/0140039 (2002-10-01), Adkisson et al.
patent: 2002/0153587 (2002-10-01), Adkisson et al.
patent: 2002/0180486 (2002-12-01), Yamashita et al.
patent: 2002/0187610 (2002-12-01), Furukawa et al.
patent: 2003/0058001 (2003-03-01), Boerstler et al.
patent: 2003/0089930 (2003-05-01), Zhao
van Meer et al., “70 nm Fully-Depleted SOI CMOS Using a New Fabrication Scheme: The Spacer/Replacer Scheme,” 2002 IEEE, 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 170-171.
Baze et al., “A Digital CMOS Design Technique for SEU Hardening,” IEEE Transactions on Nuclear Science, vol. 47, No. 6, Dec. 2000, pp. 2603-2608.
Khare et al., “A High Performance 90nm SOI Technology with 0.992 μm26T-SRAM Cell,” 2002 IEEE, pp. 16.1.1-16.1.4.
Ootsuka et al., “A Novel 0.20 μm Full CMOS SRAM Cell Using Stacked Cross Couple with Enhanced Soft Error Immunity,” 1998 IEEE, pp. 8.3.1-8.3.4.
Cox et al., “A Partially Depleted 1.8V SOI CMOS SRAM Technology Featuring a 3.77 μm2Cell,” 2000 IEEE, 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 170-171.
Ikeda et al., “A Soft Error Immune 0.35 μm PD-SOI SRAM Technology Compatible with Bulk CMOS,” Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 159-160.
Warren et al., “Analysis of the Influence of MOS Device Geometry on Predicted SEU Cross Sections,” IEEE Transactions on Nuclear Science, vol. 46, No. 6, Dec. 1999, pp. 1363-1369.
Dodd et al., “Basic Mechanisms and Modeling of Single-Event Upset in Digital Microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, No. 3, Jun. 2003, pp. 583-602.
Schwank et al., “BUSFET—A Radiation-Hardened SOI Transistor,” IEEE Transactions on Nuclear Science, vol. 46, No. 6, Dec. 1999, pp. 1809-1816.
Shaneyfelt et al., “Challenges in Hardening Technologies Using Shallow-Trench Isolation,” IEEE Transactions on Nuclear Science, vol. 45, No. 6, Dec. 1998, pp. 2584-2592.
Gasiot et al., “Comparison of the Sensitivity to Heavy Ions of 0.25-μm Bulk and SOI Technologies,” IEEE Transactions on Nuclear Science, vol. 49, No. 3, Jun. 2002, pp. 1450-1455.
Sung et al., “Design of an Embedded Fully-Depleted SOI SRAM,” 2001 IEEE, pp. 13-18.
Zhang, et al., “Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance Nano-Scale Circuit Design,” pp. 213-218.
Brady et al., “Evaluation of the Performance and Reliability of a 1M SRAM on Fully-Depleted SOI,” Proceedings 1998 IEEE International SOI Conference, Oct. 1998, pp. 129-130.
Hirano et al., “High Soft-Error Tolerance Body-Tied SOI Technology with Partial Trench Isolation (PTI) for Next Generation Devices,” 2002 IEEE, 2002 Symposium On VLSI Technology Digest of Technical Papers, pp. 48-49.
Hirano et al., “Impact of Actively Body-bias Controlled (ABC) SOI SRAM by using Direct Body Contact Technology for Low-Voltage Application,” 2003 IEEE, pp. 2.4.1-2.4.4.
Hazucha et al., “Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate,” IEEE Transactions on Nuclear Science, vol. 47, No. 6, Dec. 2000, pp. 2586-2594.
Leray et al., “Impact of Technology Scalings in SOI Back-Channel Total Dose Tolerance, a 2-D Numerical Study Using Self-Consistent Oxide Code,” IEEE Transactions on Nuclear Science, vol. 47, No. 3, Jun. 2000, pp. 620-626.
Tosaka et al., “Measurement and Analysis of Neutron-Induced Soft Errors in Sub-Half-Micron CMOS Circuits,” IEEE Transactions on Electron Devices, vol. 45, No. 7, Jul. 1998, pp. 1453-1458.
Sexton et al., “Precursor Ion Damage and Angular Dependence of Single Event Gate Rupture in Thin Oxides,” IEEE Transactions on Nuclear Science, vol. 45, No. 6, Dec. 1998, pp. 2509-2518.
Liu et al., “Proton Induced Single Event Upset In A 4M SOI SRAM,” 2003 IEEE, pp. 26-27.
Schwank et al., “Radiation Effects in SOI Technologies,” IEEE Transactions on Nuclear Science, vol. 50, No. 3, Jun. 2003, pp. 522-538.
Hirose et al., “SEU Resistance in Advanced SOI-SRAMs Fabricated by Commercial Technology Using a Rad-Hard Circuit Design,” IEEE Transactions on Nuclear Science, vol. 49, No. 6, Dec. 2002, pp. 2965-2968.
Dodd et al., “SEU-Sensitive Volumes in Bulk and SOI SRAMs From First-Principles Calculations and Experiments,” IEEE Transactions on Nuclear Science, vol. 48, No. 6, Dec. 2001, pp. 1893-1903.
Gasiot et al., “SEU Sensitivity of Bulk and SOI Technologies to 14-MeV Neutrons,” IEEE Transactions on Nuclear Science, vol. 49, No. 6, Dec. 2002, pp. 3032-3037.
Dodd et al., “Single-Event Upset and Snapback in Silicon-on-insulator Devices and Integrated Circuits,” IEEE Transactions on Nuclear Science, vol. 47, No. 6, Dec. 2000, pp. 2165-2174.
Cohen et al., “Soft Error Considerations for Deep-Submicron CMOS Circuit Applications,” 1999 IEEE, pp. 13.1.1-13.1.4.
Milanowski et al., “TCAD-Assisted Analysis of Back-Channel Leakage in Irradiated Mesa SOI nMOSFETs,” IEEE Transactions on Nuclear Science, vol. 45, No. 6, Dec. 1998, pp. 2593-2599.
Ferlet-Cavrois et al., “Total Dose Induced Latch in Short Channel NMOS/SOI Transistors,” IEEE Transactions on Nuclear Science, vol. 45, No. 6, Dec. 1998, pp. 2458-2466.
Ferlet-Cavrois et al., “Worst-Case Bias During Total Dose Irradiation of SOI Transistors,” IEEE Transactions on Nuclear Science, vol. 47, No. 6, Dec. 2000, pp. 2183-2188.
Harada et al., “2-GHz RF Front-End Circuits in CMOS/SIMOX Operating at an Extremely Low Voltage of 0.5 V,” IEEE Journal of Solid-State Circuits, vol. 35, No. 12, Dec. 2000, pp. 2000-2004.
Wann et al., “CMOS with Active Well Bias for Low-Power and RF/Analog Applications,&

Affiliated with

Also associated with

Rating

SRAM cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3412632