SRAM bus architecture and interconnect to an FPGA

Details SRAM bus architecture and interconnect to an FPGA SRAM bus architecture and interconnect to an FPGA

2006-12-05

2006-12-05

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S305000, C326S039000

Reexamination Certificate

active

07146441

ABSTRACT:
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

REFERENCES:
patent: 5861761 (1999-01-01), Kean
patent: 6018490 (2000-01-01), Cliff et al.
patent: 6028809 (2000-02-01), Schleicher et al.
patent: 6038627 (2000-03-01), Plants
patent: 6049487 (2000-04-01), Plants et al.
patent: 6104208 (2000-08-01), Rangasayee
patent: 6160419 (2000-12-01), Veenstra et al.
patent: 6181159 (2001-01-01), Rangasayee
patent: 6249143 (2001-06-01), Zaveri et al.
patent: 6326807 (2001-12-01), Veenstra et al.
patent: 6329839 (2001-12-01), Pani et al.
patent: 6496887 (2002-12-01), Plants
patent: 6799240 (2004-09-01), Plants
“SRAM based re-programmable FPGA for space applications” by Wang et al. (abstract only) publication
Publication Date: Dec. 1999.
“Intel's FLEXlogic architecture” by Smith, D.E. (abstract only) Publication Date: Feb. 22-26, 1993.

Affiliated with

Also associated with

Rating

SRAM bus architecture and interconnect to an FPGA does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with SRAM bus architecture and interconnect to an FPGA, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM bus architecture and interconnect to an FPGA will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3670143