Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2006-05-30
2006-05-30
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S305000, C710S316000, C326S037000, C326S038000, C326S039000, C365S185010, C365S185110, C711S104000, C716S030000
Reexamination Certificate
active
07054967
ABSTRACT:
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.
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“SRAM based re-programmable FPGA for space applications” by Wang et al. (abstract only) Publication Date: Dec. 1999.
“Intel's FLEXlogic FPGA architecture” by Smith, D.E. (abstract only) Publication Date: Feb. 22-26, 1993.
Actel Corporation
Ray Gopal C.
Sierra Patent Group Ltd.
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