Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-07-21
2002-09-03
Sherry, Michael (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
Reexamination Certificate
active
06445002
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor integrated circuit devices of multiple types, devices of each type being manufactured in a small number, and more particularly to a failure-ratio estimating method for estimating the failure-ratio of the devices of each type on the market and setting appropriate initial-failure screening conditions, and said method is employed when multiple types of semiconductor integrated circuit devices are developed and mass-produced. The invention also relates to a method for manufacturing the above-described semiconductor integrated devices, and to a semiconductor integrated circuit device for testing.
The process will be stated below, which is used for developing semiconductor integrated circuit devices (hereinafter referred to as “semiconductor devices”) of multiple types, devices of each type being manufactured in a small number, such as ASICs (Application Specific ICs), and then mass-producing the developed devices.
First, the types of devices to be developed are determined. After determining the to-be-developed types of devices, it is determined what structure the testing semiconductor devices should have. After that, the degree of reliability demanded for transistors, aluminum wirings, contacts, etc. incorporated in a testing semiconductor device is determined. Then, the degree of reliability demanded for the entire testing semiconductor device is determined, which is the final step in the development process. Subsequently, integrated circuits are formed on a semiconductor wafer by performing treatments of thin film forming, exposure, etching, etc. Thereafter, an assembly process which includes the steps of dicing, bonding, packaging, etc. is performed to complete the testing semiconductor devices or testing products. The resultant testing products are analyzed to thereby estimate the reliability of the products and hence of semiconductor devices to be manufactured. The above-described steps are included in the development stage. Reliability estimation of semiconductor devices is performed as occasion demands in the development stage, and the estimation results are reflected in the mass production stage. The reliability estimation of semiconductor devices is based on the estimation of their failure ratio on the market.
Parallel to the development, mass production of products
1
,
2
, . . . , n is sequentially performed. In the manufacture of the products
1
, mask forming, sample shipment and mass production are sequentially executed. The same can be said of the other products
2
,
3
, . . . , n.
In the conventional development and mass production of semiconductor devices of multiple types, devices of each type being manufactured in a small number, the devices of each type are subjected to an acceleration test to thereby estimate their failure ratio on the market and carry out appropriate initial-failure screening. Accordingly, a lot of time and effort are required for the development, and it is difficult to optimize the initial-failure screening in the mass production stage. This makes it difficult to obtain reliable products in a stable manner. Under these circumstances, it is demanded to reduce the time and effort required for the development, and to construct a system for optimizing the initial-failure screening conditions for dealing with an increase or decrease in the failure ratio on the market after the mass production stage, thereby providing highly reliable products.
BRIEF SUMMARY OF THE INVENTION
It is the object of the invention to provide a semiconductor integrated circuit device which can be developed with a reduction in time and effort, a method for manufacturing the device, a semiconductor integrated circuit device for testing, and a method for estimating the failure-ratio of semiconductor integrated circuit devices on the market, which employs a system for optimizing the initial-failure screening conditions for dealing with an increase or decrease in the failure ratio on the market after the mass production stage.
According to a first aspect of the present invention, there is provided a method of estimating the failure ratio of semiconductor integrated circuit devices on the market, comprising the steps of:
classifying semiconductor integrated circuit devices of multiple types into a plurality of type groups;
subjecting semiconductor integrated circuit devices of a representative type from each type group, to an acceleration test, and estimating the failure ratio on the market of the semiconductor integrated circuit devices of the representative type on the basis of the result of the acceleration test; and
estimating the failure ratio on the market of semiconductor integrated circuit devices of any other type from the each type group, on the basis of the first-estimated failure ratio on the market.
In the method of estimating the failure ratio of semiconductor integrated circuit devices on the market according to the first aspect of the present invention, a plurality of types included in each type group may have a common main feature. The common main feature may include at least one of a design rule, a MOS structure and a wiring structure. In the step of estimating the failure ratio on the market of semiconductor integrated circuit devices of the representative type, failure causes of those ones of the semiconductor integrated circuits of the representative type, which have failed during the acceleration test, may be determined by an analysis using a tester, thereby determining, for each of the failure causes, the failure ratio on the market of the semiconductor integrated circuit devices under conditions of the acceleration test. In the step of estimating the failure ratio on the market of the semiconductor integrated circuit devices of the any other type, the failure ratio on the market of semiconductor integrated circuit devices of the each type from the each type group, which is obtained under corresponding expected conditions of use, may be estimated for each of the failure causes, in correspondence to a scale of the semiconductor integrated circuit devices of the each type, using the estimated failure ratio on the market of the semiconductor integrated circuit devices of the representative type for each of the failure causes, and the sum of the estimated failure ratios for the failure causes may be considered the failure ratio of the semiconductor integrated circuit device of the each type.
In the method of estimating the failure ratio of semiconductor integrated circuit devices on the market according to the first aspect of the present invention, in the step of estimating the failure ratio on the market of semiconductor integrated circuit devices of the representative type, failure causes of those ones of the semiconductor integrated circuits of the representative type, which have failed in the acceleration test, may be determined by an analysis using a tester, thereby determining, for each of the failure causes, the failure ratio on the market of the semiconductor integrated circuit devices under conditions of the acceleration test. A testing semiconductor integrated circuit device may be used as each of the semiconductor integrated circuit devices of the representative type. The testing semiconductor integrated circuit device may have a SRAM block array of MOS transistors. The SRAM block array may include twelve MOS transistors. The SRAM block array may include six MOS transistors. No metal wiring may extend on gates of the MOS transistors. The testing semiconductor integrated circuit device may have a sufficiently greater gate area, a sufficiently greater wiring length and a sufficiently greater number of contact holes than an average gate area, an average wiring length and an average number of contact holes of semiconductor integrated circuit products of each of a plurality of groups of types, respectively, the gate, the wiring length and the contact holes in the semiconductor integrated circuit products of the each group being a common main feature. In the step of estimating the fail
Asami Tetsuya
Hashimoto Takehiro
Okumiya Noriaki
Satou Youichi
Tanaka Yutaka
Kabushiki Kaisha Toshiba
Pert Evan
Sherry Michael
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