SRAM architecture

Details SRAM architecture SRAM architecture

2011-08-30

2011-08-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S230050

Reexamination Certificate

active

08009462

ABSTRACT:
A SRAM architecture includes a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB(bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.

REFERENCES:
patent: 5946251 (1999-08-01), Sato et al.
patent: 5973984 (1999-10-01), Nagaoka
patent: 7414903 (2008-08-01), Noda

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