Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
1998-10-29
2001-10-30
Nguyen, Nam (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S192250, C438S592000, C438S649000, C438S682000
Reexamination Certificate
active
06309515
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a sputtering apparatus for sputtering a high melting point metal, and more particularly a method for manufacturing a MOS type field effect transistor (MOSFET) producing a low resistance by making a silicide of each of the surfaces of the gate, source and drain surfaces in a self-coincidence manner. In addition, the present invention relates to a sputtering apparatus in which metal with high melting point can be sputtered on a poly-crystalline-silicon film in such a way that an insulating withstand voltage deterioration in a gate oxidation film may not be produced when a high melting point metallic silicide which is constitutive of metal with high melting point film is formed at a gate electrode.
2. Description of the Prior Art
As the prior art silicide process known as one of the methods for manufacturing semiconductor device, there is provided a method disclosed in Japanese Patent Application No. Hei 2-45923. Referring now to longitudinal sections of FIGS.
3
A to
3
D in an order of steps, this prior art method for manufacturing the semiconductor device will be described.
As shown in
FIG. 3A
, an N-well
302
is formed at a P-type silicon substrate
301
by a well-known method. Then, a field oxidation film
303
is formed as a field insulating film at the surface of the P-type silicon substrate
301
by a selective oxidation process. A gate insulating film
304
such as a silicon oxidation film or the like and a poly-crystalline silicon are grown in an active region enclosed by this field oxidation film
303
, phosphorus is doped by a well-known process to reduce an electrical resistance of the poly-crystalline silicon. Then, the poly-crystalline silicon is processed with patterning to form a gate electrode
305
by well-known processes of a photo-lithography and a dry etching.
Then, an N-type impurities dispersion layer
313
of low concentration and a P-type impurities dispersion layer
314
of low concentration are formed by the photo-lithography and an ion implanting process as shown in FIG.
3
A. Then, a side wall (a spacer)
306
constituted by a silicon oxidation film or silicon nitride film is formed at a side surface of the gate electrode
305
by a well-known chemical vapour development (CVD) technology and an etching technology.
Then, an N-type impurities dispersion layer
307
and a P-type impurities dispersion layer
308
are formed by the photo-lithography and the ion implanting process as shown in FIG.
3
B. In this way, as an LDD structure, an N-type source drain region
307
and a P-type source drain region
308
are formed. Then, natural oxidation film at the surface of the poly-crystalline silicon and the surface of the semiconductor substrate is removed, for example, a titanium film
309
is accumulated in sputtering process.
Then, as shown in
FIG. 3C
, a fast heat treatment (hereinafter called as RTA) at 700° C. under nitrogen atmosphere is carried out, thereby only the titanium film
309
contacted with silicon is changed into silicide so as to form a titanium silicide layer
310
of C49 type structure. In addition, in this case, the titanium film
309
contacted with the field oxidation film
303
and the spacer
306
and a part of the titanium film on the semiconductor substrate are nitrided to become a titanium nitride film
311
.
Then, as shown in
FIG. 3D
, it is processed selectively with wet etching by mixture solution such as ammonia solution and hydrogen peroxide solution and the like so as to remove only not-yet reacted titanium and the titanium nitride film
311
. Then, RTA at a higher temperature (800° C. or more) than the aforesaid RTA is carried out to form a titanium silicide layer
312
of C54 type structure having a lower electric resistibility than that of the aforesaid titanium silicide layer
310
of C49 type structure.
Application of the aforesaid silicide process causes the surfaces of the poly-crystalline silicon
305
, N-type and P-type impurities dispersion layers
307
,
308
to be changed into silicide in a self-alignment manner and to have a low resistance and then a high speed in operation of the device can be attained. This silicide forming process has an advantage in which only the required region can be selectively reached to silicide.
In this case, a magnetron sputtering apparatus
10
(of
FIG. 8
) shown in the prior art is in general provided with a wafer holder
14
for use in mounting a wafer W within a sputter chamber
12
and a cathode magnet
16
for holding a target T at a position spaced apart and oppositely faced against the wafer W as shown in FIG.
8
.
In the case that Co was sputtered on a polycrystalline-silicon gate electrode, for example, under application of the prior art magnetron sputtering apparatus
10
(of
FIG. 8
) to form a Co silicide electrode, the chip having poor electric insulation state at the gate oxidation film was generated on the wafer, a large amount of chips were produced around the wafer in particular, resulting in that a certain problem occurred in view of improving yield of product.
This paragraph shows a test result performed under an application of the prior art magnetron sputtering apparatus
10
(of
FIG. 8
) wherein Co was sputtered on poly-crystalline-silicon of the gate electrode in the following sputtering condition to form a Co film, then RTA was applied to make a Co silicide, thereafter a state of insulating withstand voltage at the gate oxidization film was tested for every chip of wafer.
In this test, the prior art magnetron sputtering apparatus
10
is applied, Co is sputtered on the poly-crystalline-silicon film
22
of the gate electrode formed on the silicon substrate
20
to form a Co film
24
and then RTA is applied to form a Co silicide layer as shown in FIG.
9
.
FIG. 9
shows a state in which the Co film
24
is formed on the polycrystalline-silicon film
22
of the gate electrode by a sputtering process. In
FIG. 9
, reference numeral
26
denotes a spacer and reference numeral
28
denotes a gate oxidation film.
Sputtering Condition
Chamber pressure: 5 to 15 mTorr
Gas flow rate: Ar/50 to 100 scc/m
Sputtering power: 1.5 kW
However, the Co sputtering under application of the prior art magnetron sputtering apparatus
10
showed that a poor insulation was produced at the gate oxidation film of the chip at a peripheral part of the wafer as shown in
FIG. 11
, a percentage of a superior chip having an insulating withstand voltage of the gate oxidation film more than a predetermined value in respect to entire chips of the wafer, a so-called yield rate was about 46% as indicated by combined results of the example of experiment 1 and the example of experiment 2 in FIG.
19
.
In
FIG. 11
, the chip having a high degree of poor insulation at the gate oxidation film is colored in black and the chip having a low degree of poor insulation is colored in gray (no such regions shown in FIG.
11
).
However, the aforesaid prior art method for manufacturing a semiconductor device has a problem that after forming a gate polycrystalline-silicon, a high melting point metal is sputtered and accumulated on the gate polycrystalline-silicon, resulting in that the gate electrode
305
is charged up by an electrical load generated from plasma and then the gate withstand voltage becomes deteriorated.
As a method for forming silicide only on the gate electrode and the dispersion layer, although this method is an effective one in view of silicide formation process, the ground structure applied when the metal with high melting point is sputtered is set such that a natural oxidation film at the surface of the gate electrode
305
is removed, the gate electrode
305
is already doped with impurities, resulting in that it becomes a floating gate.
Due to this fact, it may produce a problem that a shutter is opened during a sputtering, in particular during sputtering electrical discharging or an electrical discharging at the time of waiting and an electrical load is produced at the gate electrode immediately after
Abiko Hitoshi
Higuchi Minoru
Inoue Ken
Cantelmo Gregg
Foley & Lardner
NEC Corporation
Nguyen Nam
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