Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
1998-09-14
2001-05-01
Pham, Chi (Department: 2631)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S153000
Reexamination Certificate
active
06226319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a spread spectrum demodulation circuit and spread spectrum communication apparatus for demodulating a transmission information signal from a reception signal to which a quadrature phase shift keying and a spread spectrum modulation are performed.
Further, the present invention relates to a delay-detection-type demodulation circuit and delay-detection-type communication apparatus for demodulating a transmission information signal from a reception signal to which a quadrature phase shift keying is performed.
2. Description of the Related Art
A spread spectrum communication scheme (SS communication scheme) has recently been paid attention as a private communication system, because of high resistance to noises and excellency of security and secrecy. In the SS communication scheme, a carrier wave which is phase-modulated by information to be transmitted (transmission information) is spread-spectrum-modulated (SS modulated) by a predetermined code sequence having a predetermined high chip rate, to thereby obtain a spread spectrum signal (SS signal) used as a transmission signal. The code sequence includes a pseudo noise code sequence (PN code sequence) or a Barker code sequence, and the SS modulation scheme includes a direct spread scheme (DS scheme) and a frequency hopping scheme (FH scheme).
In the SS communication system, it is necessary for a receiver to have a demodulator for demodulating the transmitted SS signal. For example, if the carrier wave is SS-modulated through the DS scheme using the PN code sequence, the receiver demodulates it by using the same PN code sequence as that used by the transmitter. A demodulator to be used for such a purpose is broadly classified into a demodulator using an IC and a demodulator using a surface acoustic wave element. The surface acoustic wave element to be used for the demodulator can be realized cost effectively and in simple structure by utilizing photolithography, and so the demodulator of this type is being paid attention.
The surface acoustic wave element is classified from its configuration into a surface acoustic wave matched filer and a surface acoustic wave convolver. Since the surface acoustic wave convolver can select the PN code sequence for demodulation, it is particularly suitable for the field where security and secrecy are required. Since the surface acoustic wave matched filter uses a fixed code sequence for demodulation, a peripheral circuit can be simplified correspondingly and the whole system can be made inexpensive. Therefore, the surface acoustic wave matched filter is being paid attention for use with a demodulator for a small SS communication system such as an intra-radio LAN. Various types of surface acoustic wave matched filters and demodulators using such matched filters have been proposed.
A conventional demodulation circuit using a surface acoustic wave matched filter compatible with a quadrature phase shift keying scheme (QPSK scheme) is shown in a block diagram of FIG.
10
.
FIG. 10
illustrates a conventional spread spectrum demodulation circuit (SS demodulation circuit). The demodulation circuit comprises a correlation signal generator
51
, a first delay element
52
a,
a first adder
53
a
for adding a correlation signal output from the correlation signal generator
51
and an output signal (first delay signal) of the first delay element
52
a,
signal lines
54
a
and
55
a,
and a first reproduction circuit
56
a
for reproducing data from an output signal (first addition signal) of the first adder
53
a.
For signal inputs to the first adder
53
a,
the delay amount of the first delay element
52
a
is set so that the input signal (first delay signal) from the first delay element
52
a
is delayed from the input signal (correlation signal) from the correlation signal generator
51
by T+(±n+5×a/8)/fc, where T represents one period of a reception signal to be demodulated, n represents an integer from “0” to a value equal to or smaller than a ratio multiplied by “2” of the carrier frequency fc of a signal input to a means for retrieving correlation signal to a chip rate, and 1/2≦a≦3/2.
The demodulation circuit further comprises a second delay element
52
b,
a second adder
53
b
for adding the correlation signal output from the correlation signal generator
51
and an output signal (second delay signal) of the second delay element
52
b,
signal lines
54
b
and
55
b,
a second reproduction circuit
56
b
for reproducing data from an output signal (second addition signal) of the second adder
53
b,
and a synthesizing circuit
57
for synthesizing output data of the first reproduction circuit
56
a
and output data of the second reproduction circuits
56
b.
A data demodulation circuit
58
is constituted of the first and second reproduction circuits
56
a
and
56
b
and the synthesizing circuit
57
. For signal inputs to the second adder
53
b,
the delay amount of the second delay element
52
b
is set so that the input signal (second delay signal) from the second delay element
52
b
is delayed from the input signal (correlation signal) from the correlation signal generator
51
by T+(±m−5×a/8)/fc, where m represents an integer from “0” to a value equal to or smaller than a ratio multiplied by “2” of a carrier frequency fc of a signal input to a means for retrieving correlation signal to a chip rate. It is preferable that n=0, m=0, and a=1.
FIG. 11
is a phase transition diagram showing the phase states of the surface acoustic wave matched filer and delay elements during demodulation of a signal compatible with the QPSK scheme. In
FIG. 11
, (A, B, C, D) indicates four phase states, i.e. A(
10
), B(
00
), C(
01
) and D(
11
), corresponding to the QPSK scheme in the output signal of the surface acoustic wave matched filter. Assuming that a=1, (A′, B′, C′, D′) indicates the phase states of the signal delayed in the first delay element
52
a
by T+(±n+⅝)/fc, and (A″, B″, C″, D″) indicates the phase states of the signal delayed in the second delay element
52
b
by T+(±m−⅝)/fc. For example, when the signal in the state A is delayed in the first delay element
52
a
by T+(±n+⅝)/fc, the state A transits to the state A′. When the signal in the state A is delayed in the second delay element
52
b
by T+(±m−⅝)/fc, the state A transits to the state A″.
In
FIG. 12
, (a) illustrates a timing of the information signal to be transmitted (transmission information signal) D
21
; (b) illustrates a timing of a signal D
22
which is obtained by subjecting the differential coding (to be later described) to the transmission information signal D
21
; (c) illustrates a timing of a correlation signal S
21
output from the correlation signal generator
51
; (d) illustrates a timing of a first delay signal S
22
delayed in the first delay element
52
a
by T+(±n+⅝)/fc; (e) illustrates a timing of a first addition signal S
23
obtained by adding the correlation signal S
21
and the first delay signal S
22
; (f) illustrates a timing of data D
23
reproduced from the first addition signal S
23
in the first reproduction circuit
56
a;
(g) illustrates a timing of a second delay signal S
24
delayed in the second delay element
52
b
by T+(±m−⅝)/fc; (h) illustrates a timing of a second addition signal S
25
obtained by adding the correlation signal S
21
and the second delay signal S
24
; (i) illustrates a timing of data D
24
reproduced from the second addition signal S
25
in the second reproduction circuit
56
b;
(j) illustrates a timing of an information signal D
25
obtained by synthesizing in the synthesizing circuit
57
the data D
23
reproduced in the first reproduction circuit
56
a
and the data D
24
reproduced in the second reproduction cir
Koga Naoki
Ohtsuka Masatoshi
Frank Robert J.
Lachhab Mohammed
Matsushita Electric - Industrial Co., Ltd.
Pham Chi
Venable
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