Spray cooling and transparent cooling plate thermal...

Details Spray cooling and transparent cooling plate thermal... Spray cooling and transparent cooling plate thermal...

2003-03-04

2004-12-28

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C438S016000

Reexamination Certificate

active

06836131

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and a method for thermal management of an electrically stimulated semiconductor integrated circuit undergoing probing, diagnostics, or failure analysis.
2. Description of the Related Art
Integrated circuits (ICs) are being used in increasing numbers of consumer devices, apart from the well-known personal computer itself. Examples include automobiles, communication devices, and smart homes (dishwashers, furnaces, refrigerators, etc.). This widespread adoption has also resulted in ever larger numbers of ICs being manufactured each year. With increased IC production comes the possibility of increased IC failure, as well as the need for fast and accurate chip probing, debug, and failure analysis technologies. The primary purpose of today's probing, debug, and failure analysis systems is to characterize the gate-level performance of the chip under evaluation, and to identify the location and cause of any operational faults.
In the past, mechanical probes were used to quantify the electrical switching activity. Due to the extremely high circuit densities, speeds, and complexities of today's chips, including the use of flip-chip technology, it is now physically impossible to probe the chips mechanically without destructively disassembling them. Thus, it is now necessary to use non-invasive probing techniques for chip diagnostics. Such techniques involve, for example, laser-based approaches to measure the electric fields in silicon, or optically-based techniques that detect weak light pulses that are emitted from switching devices, e.g., field-effect transistors (FETs), during switching. Examples of typical microscopes for such investigations are described in, for example, U.S. Pat. Nos. 4,680,635; 4,811,090; 5,475,316; 5,940,545 and Analysis of Product Hot Electron Problems by Gated Emission Microscope, Khurana et al., IEEE/IRPS (1986), which are incorporated herein by reference.
During chip testing, the chip is typically exercised at relatively high speeds by a tester or other stimulating circuit. Such activity results in considerable heat generation. When the device is encapsulated and is operated in its normal environment, various mechanisms are provided to assist in heat dissipation. For example, metallic fins are often attached to the IC, and cooling fans are provided to enhance air flow over the IC. However, when the device is under test, the device is not encapsulated and, typically, its substrate is thinned down for testing purposes. Consequently, no means for heat dissipation are available and the device under test (DUT) may operate under excessive heat so as to distort the tests, and may ultimately fail prematurely. Therefore, there is a need for effective thermal management of the DUT.
One prior art system used to cool the DUT is depicted in
FIG. 1
a
. The cooling device
100
consists of a cooling plate
110
having a window
135
to enable optical probing of the DUT. The window
135
may be a simple cut out, or may be made of thermally conductive transparent material, such as synthetic diamond. The use of synthetic diamond to enhance cooling is described in, for example, U.S. Pat. No. 5,070,040, which is incorporated herein by reference. Such a solid transparent window is often referred to as a transparent heat spreader. Conduits
120
are affixed to the cooling plate
110
for circulation of cooling liquid. Alternatively, the conduits may be formed as an integral part of the plate, see, e.g., U.S. Pat. No. 6,140,141.
FIG. 1
a
depicts in broken line a microscope objective
105
used for the optical inspection, and situated in alignment with the window
135
. During testing, the cooling plate is placed on the exposed surface of the DUT
160
, with the window
135
placed over the location of interest. When the cooling plate
110
is used with a transparent heat spreader
135
, an oil layer, or other high index of refraction fluid, is sometimes provided between the transparent heat spreader
135
and the DUT
160
in order to improve the optical coupling from the DUT
160
to the transparent heat spreader
135
. Heat from the device is conducted by the cooling plate to the conduits and the cooling liquid. The cooling liquid is then made to circulate through a liquid temperature conditioning system, such as a chiller, thereby removing the heat from the device. Typically, however, the DUT includes auxiliary devices
165
, which limit the available motion of the cooling plate, thereby limiting the area available for probing. To overcome this, custom plates are made for specific devices, leading to increased cost and complexity of operation of the tester.
Another problem with the conventional cooling plate is insufficient and non-uniform heat removal from the DUT.
FIGS. 1
b
and
1
c
schematically show a conventional cooling plate with a transparent heat spreader of a somewhat modified design from that of
FIG. 1
a
.
FIG. 1
b
is a top view, while
FIG. 1
c
is a partial cross section along lines A—A in
FIG. 1
b
. A transparent heat spreader
110
′ is soldered to a frame
130
using, for example, an indium solder at interface
115
. A DUT (not shown) is observable through transparent heat spreader
110
′, and oil or other fluid may be provided between the DUT and the heat spreader. The frame
130
is attached to, or is formed as an integral part of, an inner metallic heat sink
140
which, in turn, is attached to an outer metallic heat sink
150
. Conventionally, the inner metallic heat sink
140
is attached to the outer metallic heat sink
150
using screws and having no heat conducting material there-between. Chilled air is pumped through inlet
170
to circulate through the outer metallic heat sink
150
, and is exhausted through outlet
175
.
As can be understood, heat is transported from the DUT to the transparent heat spreader
110
′, to the frame
130
, to the inner metallic heat sink
140
, to the outer metallic heat sink
150
, and to the chilled fluid. However, the interfaces between the various elements act to resist heat conduction, thereby reducing the efficiency of heat removal from the DUT. Additionally, the temperature gradient across the various elements encourages heat gain from the ambient. In fact, studies have shown that heat gain from the ambient can be greater than the heat removal from the DUT. The thermal resistance present in the heat conduction path, along with the significant heat gained from the ambient, combine to dramatically increase the difficulty in lowering the temperature of the transparent heat spreader and, thereby, lowering the temperature of the DUT.
Of particular interest to the present inventors is the temperature at the periphery of the transparent heat spreader (locations of
1
-
8
in
FIG. 1
b
). That is, the inventors speculated that a system having efficient heat transport will lower the temperature at the periphery of the transparent heat spreader, and thereby the temperature of the heat spreader and the DUT. To investigate that, a temperature distribution of an industry standard semiconductor thermal test chip, cooled by transparent heat spreader as exemplified in
FIG. 1
b
, was simulated using a Finite Element model. The model simulated the temperature distribution in the transparent heat spreader, as well as the heat conduction from the transparent heat spreader, across the indium solder, to the periphery of the inner metallic heat sink. Using a one dimensional heat conduction analysis to calculate the temperature rise from the surface of the transparent heat spreader to the chip, the chip's temperature distribution, and its maximum temperature, were determined. The accuracy of the prediction of the Finite Element model is directly tied to the accuracy of the imposed boundary conditions. In this case, a key boundary condition is the temperature at the inner periphery of the inner metallic heat sink, i.e., at the indium solder contact area. As can be understood, the temperature at this perip

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