Splitting grouped writes to different memory blocks

Details Splitting grouped writes to different memory blocks Splitting grouped writes to different memory blocks

2001-05-18

2003-12-09

Tung, Kee M. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Addressing

C345S531000, C711S201000

Reexamination Certificate

active

06661423

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to graphics frame buffer architecture.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data rates places additional burden on the memory systems that form an integral part of the graphics system. Attempts to further improve graphics system performance are now running up against the limitations of these memory systems in general, and memory device limitations in particular.
In order to provide memory systems with increased data handling rates, system architects may employ a form of memory architecture known as tessellated memory. In a tessellated memory design, a single read or write operation to the memory array results in the retrieval or storage of a group of data elements or tiles. In general, such a tessellated memory is optimized for the storage and retrieval of tiles having fixed dimensions and boundaries which are stationary (i.e. with respect to word boundaries within the memory array). The design of such a memory is well known in the art. For example, the 3D-RAM memory from Mitsubishi corporation may be used to implement one such tessellated memory.
Unfortunately, problems often arise in the implementation of tessellated memories when the tiles to be stored or retrieved are not stationary within the address space of the memory. For example, in a generalized graphics system, graphical elements may be drawn using supersamples, (i.e., picture elements which are submultiples of the display pixels). To increase system throughput, these supersamples may grouped into tiles for storage in a frame buffer. If the supersamples have no immediate correlation to a fixed reference, such as displayable pixels, it is possible that the boundaries of the supersample tiles may be misaligned with the tiles of the tessellated memory. If a misalignment occurs, then the storage of the tile fails, (i.e., the elements of the tile are not stored coherently within the memory array). For these reasons, a system and method for storing misaligned data to graphics system memory is desired.
SUMMARY OF THE INVENTION
The problems set forth above may at least in part be solved in some embodiments by a system or method for detecting memory block boundary violations and splitting tiled graphics data accordingly. In one embodiment, the system may include a memory configured to receive and store tiles of graphics data. The memory may be further configured as an array of storage devices, allowing for an entire tile of graphics data to be written in a single operation. In some embodiments, this array may include 3D-RAM devices. A boundary violation detector may be connected to the memory, and may be configured to examine the target address of a single unit of graphics data within the tile in order to determine whether the entire tile falls within the block boundaries of the memory. A write controller may also be connected to the memory and to the boundary violation detector, and may be configured to employ the boundary violation information to generate a sequence of storage operations to the memory according to the number of boundaries violated.
As noted above, a method for detecting memory block boundary violations is also contemplated. In one embodiment, the method includes dividing the target address into fields which describe the dimensions of a memory block, and the number of horizontal and vertical memory blocks contained in the memory. Next, a value which correlates to the size of the tile may then be added to the fields describing the memory block dimensions. A modulo operation may then be performed on the results of the addition where the memory block dimensions are used for the modulus. If the result of a modulo operation is zero, then the associated boundary violation is indicated. The boundary violations may then be used to split the tile accordingly. A horizontal boundary violation may cause the tile to be split into two sub-tiles along a vertical axis, whereas vertical boundary violation may cause the tile to be split into two sub-tiles along a horizontal axis. If both boundaries are violated, then the tile may be split along both the horizontal and vertical axis, resulting in four sub-tiles.
In one embodiment, the system may be integrated into a graphics system suitable for creating and displaying graphic images. In other embodiments, the system may be part of an optional assembly, communicating with a host graphics system through the use of a data or control bus specific to the host.


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“Memory management support for titled array organization” by Gary Newman, Computer Architecture News, vol. 20, No. 4, 9/92 pp. 2-30.

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