Splitting execution of a floating-point add instruction...

Details Splitting execution of a floating-point add instruction... Splitting execution of a floating-point add instruction...

2005-07-21

2009-08-11

Huisman, David J (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C708S505000

Reexamination Certificate

active

07574584

ABSTRACT:
In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to software and partly in the hardware state machine. For a floating point add instruction, mantissa addition is executed in the integer pipeline and the plurality of operations performed by the hardware state machine includes testing of exponents, testing for overflow and underflow conditions, packing, and rounding detection.

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