Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-05-09
2008-05-27
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S593000, C257S413000
Reexamination Certificate
active
07378336
ABSTRACT:
A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2or SixGeyOzinterfacial layer of 3 to 4 A thick. The thin SiO2or SixGeyOzinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
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Chan Kevin K.
Chen Jia
Huang Shih-Fen
Nowak Edward J.
Cao Phat X.
International Business Machines - Corporation
Jordan John A.
Kalam Adul
Steinberg William H.
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