Split gate type memory cell having gate insulating layers...

Details Split gate type memory cell having gate insulating layers... Split gate type memory cell having gate insulating layers...

1999-02-25

2002-11-26

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S317000, C257S318000

Reexamination Certificate

active

06486507

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor non-volatile memory device such as, for example, an electrically erasable and programmable read only memory device and, more particularly, to a split gate type memory cell of the semiconductor non-volatile memory device and a process of fabrication thereof.
DESCRIPTION OF THE RELATED ART
A stacked gate type memory transistor is a typical example of a semiconductor non-volatile memory transistor. The stacked gate type memory transistor has a floating gate over a channel region between the source/drain regions, and a gate insulting layer and a control gate are laminated on the floating gate. The stacked gate type memory transistor stores a data bit in the form of accumulated electrons injected into the floating gate electrode. If the electrons are injected into the floating gate electrode, the accumulated electrons induce holes in the channel region, and make the threshold of the stacked gate type memory transistor high. As a result, the stacked type memory transistor does not turn on under application of a read voltage to the control electrode. On the other hand, when the accumulated electrons are evacuated from the floating gate electrode, the threshold is lowered, and the read voltage causes the stacked type memory transistor to turn on. Thus, the stacked type memory transistor takes two kinds of state depending upon the amount of accumulated electrons, and two logic levels of a data bit are respectively corresponding to the two kinds of state. In the following description, one of the two kinds of state accumulating a large amount of electrons and the other kinds of state accumulating a small amount of electrons are hereinbelow referred to as “write-in state” and “erased state”, respectively.
The stacked gate type memory transistor is connected in series to a standard field effect transistor, and form in combination a split gate type non-volatile memory cell. The split gate type non-volatile memory cell is effective against over-erased state. If the accumulated electrons are excessively erased from the floating gate electrode, the stacked gate type memory transistor enters into the depletion state, and is not appropriate to store a data bit. The split gate type memory cell is well known to a person skilled in the art, and no further description is incorporated hereinbelow.
The split gate type memory cell is fabricated as follows.
FIGS. 1A
to
1
E illustrate the prior art process for fabricating the split gate type memory cell.
FIG. 1E
shows the structure along a cross section perpendicular to the cross section for
FIGS. 1A
to
1
D. The process starts with preparation of a p-type silicon substrate
1
. Boron is ion implanted into a certain area assigned to the split gate type memory cells at dosage of
3
E
13
atom/square-cm for adjusting channel dopant concentration to a target value, and, thereafter, arsenic is selectively ion implanted into the area for forming striped impurity regions
2
a
/
2
b
as shown in FIG.
1
A. The striped impurity regions
2
a
/
2
b
serve as digital lines, and parts of the digit line serve as n-type source/drain regions of a split gate type memory cell.
Silicon oxide is deposited over the entire surface of the p-type silicon substrate
1
by using a chemical vapor deposition, and the silicon oxide layer is selectively etched away in order to expose active areas of the p-type silicon substrate
1
. The remaining silicon oxide layer serves as an isolating oxide layer
3
(see FIG.
2
).
Subsequently, the active areas are thermally oxidized, and a silicon oxide layer is grown to 20 nanometers thick on the active areas. Polysilicon is deposited over the entire surface of the resultant semiconductor structure, and a photo-resist etching mask (not shown) is provided on the polysilicon layer through photo-lithographic techniques. Using the photo-resist etching mask, the polysilicon layer and the silicon oxide layer are selectively etched away, and lower gate oxide layers
4
and floating gate electrodes
5
are formed on the active areas as shown in FIG.
1
B. Each of the striped impurity regions
2
a
/
2
b
is partially overlapped with the lower gate insulating layer
4
, which is spaced from the other striped impurity region
2
b
/
2
a.
Subsequently, silicon oxide is deposited to 20 nanometers thick over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition, and forms a silicon oxide layer
6
. The resultant semiconductor structure is heated so that a silicon oxide layer
7
is grown to 20 to 30 nanometers thick on the entire surfaces of the floating gate electrodes
5
and the active areas between the floating gate electrodes
5
. The polysilicon is oxidized half as fast again as the single crystal silicon, and, for this reason, the silicon oxide layer
7
on the floating gate electrodes
5
is half as thick again as the silicon oxide layer
7
on the active areas.
Subsequently, polysilicon is deposited over the entire surface of the resultant semiconductor structure by using the chemical vapor deposition, and a polysilicon layer is formed on the silicon oxide layer
7
. Silicon oxide is deposited to 250 nanometers thick over the entire surface of the polysilicon layer by using the chemical vapor deposition, and a silicon oxide layer is laminated on the polysilicon layer. A photo-resist etching mask (not shown) is patterned on the silicon oxide layer, and has striped masking portions extending in the perpendicular direction to the striped impurity regions
2
a
/
2
b
. Using the photo-resist etching mask, the silicon oxide layer and the polysilicon layer are selectively etched away, and composite gate electrodes
8
and upper insulating layers
9
as shown in FIG.
1
D.
The composite gate electrode partially serves as control gate electrodes
10
of the stacked gate type memory transistors and partially as selecting gate electrodes
11
of the associated field effect transistors. Accordingly, the silicon oxide layers
6
/
7
under the control gate electrodes serve as upper gate oxide layers of the stacked gate type memory transistors, and the silicon oxide layers
6
/
7
under the selecting gate electrodes serve as gate oxide layers of the associated field effect transistors.
Subsequently, silicon oxide is deposited to 100 nanometers thick over the entire surface of the resultant semiconductor structure, and the silicon oxide layer is anisotropically etched without any etching mask. Side walls
12
are left on the side surfaces of the control gate electrodes
10
and the selecting gate electrodes
11
. The silicon oxide layers
6
/
7
are exposed to gaps between the side walls
12
. The silicon oxide layers
6
/
7
and the floating gate electrodes exposed to the gaps are etched away, and the isolating oxide layer
3
and side surfaces of the floating gate electrodes
5
are exposed to the gaps. Easing gate oxide layers
13
are grown to 20 nanometers thick on the side surfaces of the floating gate electrodes
5
.
Polysilicon is deposited over the entire surface of the resultant semiconductor structure. The polysilicon fills the gaps between the side walls
12
, and a polysilicon layer is spread over the silicon oxide layer
9
. Using a photo-resist etching mask, the polysilicon layer is patterned into erasing gate electrodes
14
, and the erasing gate electrodes
14
are held in contact with the erasing gate oxide layers
13
as shown in FIG.
1
E. The erasing gate electrodes
14
occupy every other gaps between the side walls
12
.
Though not shown in the drawings, the resultant semiconductor structure is covered with an inter-level insulating layer, and conductive lines are formed on the inter-level insulating layer in such a manner as to be connected through contact holes in the inter-level insulating layer to appropriate conductive portions.
In order to increase the data storing capacity of the prior art semiconductor non-volatile memory device, it is necessary to scale down the split gate type memory cell. This means that both of th

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