Split-gate thin-film storage NVM cell

Details Split-gate thin-film storage NVM cell Split-gate thin-film storage NVM cell

2002-10-30

2004-12-07

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000

Reexamination Certificate

active

06828618

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The subject invention relates generally to the design and fabrication of semiconductor devices and, more particularly, to the design and fabrication of a semiconductor nonvolatile memory (NVM) cell, wherein the NVM cell incorporates a thin film of charge-storage material for the retention of data.
2. Related Art
Semiconductor NVMs, and particularly electrically erasable, programmable read-only memories (EEPROMs), exhibit widespread applicability in a range of electronic equipments from computers, to telecommunications hardware, to consumer appliances. In general, EEPROMs serve a niche in the NVM space as a mechanism for storing firmware and data that must be refreshed periodically in situ. The EEPROM's precursor, the EPROM, can be erased only through UV irradiation and therefore requires removal from its target system prior to erasure. The flash EEPROM may be regarded as a specifically configured EEPROM that may be erased only on a global or sector-by-sector basis. The typical flash EEPROM may be divided into sectors of 64K (65, 536). The sacrifice in flash EEPROM erase selectivity is exchanged for a simplified memory cell design, which, in the limit, may require only a single MOS transistor.
As is well known to those skilled in the art, NVM cells are typically constructed by forming a field effect transistor (FET) in a body of semiconductor material, usually silicon. The FET can be made to store electrical charge (holes or electrons) in either a separate gate electrode, referred to as a floating gate, or in a dielectric layer underneath a control gate electrode. Data is stored in an NVM cell by modulating the threshold voltage, V
T
, of the FET through the injection of charge carriers from the channel of the FET. For example, with respect to an N-channel, enhancement-mode FET, an accumulation of electrons in the floating gate, or in a dielectric layer above the FET channel region, causes the FET to exhibit a relatively high V
T
. When the FET control gate is biased to the voltage required to read stored data, i.e., to a “Read” voltage, the FET will fail to conduct current because its then-existing threshold voltage is greater than the voltage applied to the gate. The nonconductive state of the FET may, by convention, be defined and detected as a logic level ZERO. Conversely, a reduction in the concentration of electrons in the floating gate, or in the dielectric layer, will cause the FET threshold voltage to diminish, and, in some designs, become negative with respect to ground. In this case, applying the Read voltage to the FET control gate will cause the FET to conduct current from drain to source. In some designs, the FET V
T
may be made negative so that an applied Read voltage of 0V will nonetheless be sufficient to cause current conduction by the FET. Current conduction by the FET may be defined and detected as a logic level ONE.
The EEPROM is encountered in numerous configurations. In general, those configurations may be classified according to (i) the nature (i.e., thickness and composition) of the layer used to store charge for V
T
modulation and (ii) the number of operative gate electrodes available to control the operation of the NVM cell. In particular, a floating-gate NVM cell is characterized by a stacked gate construction in which a floating gate, typically formed from polysilicon, is separated from the substrate by a first (lower) oxide layer and is separated from a polysilicon control gate by a second (upper) oxide layer. No direct electrical connection is made to the floating gate (hence, “floating”). A split-gate NVM cell typically exhibits two distinguishable channel regions, respectively controllable by the floating gate and the control gate, which are only partially overlapping. A discussion, not purported to be exhaustive, of known NVM configurations follows.
FIG. 1
depicts the more or less canonical configuration corresponding to a floating-gate tunnel oxide (Floating-Gate) NVM cell. The Floating-Gate cell includes a relatively thin tunneling oxide
102
interposed between a doped polysilicon floating gate
104
and a silicon substrate
100
. Tunneling oxide
102
is typically thermally grown on substrate
100
to a thickness of approximately, for example, 100 angstroms. The Floating-Gate cell further includes an oxide layer
106
overlying floating gate
104
and underlying a doped polysilicon control gate
108
. Fabrication of the Floating-Gate cell may involve successively forming layers
102
,
104
,
106
, and
108
above silicon substrate
100
. Portions of the layers not masked by a patterned photoresist layer are etched away to form the stacked structure shown in
FIG. 1. A
heavily concentrated dopant distribution that is self-aligned to the opposed sidewalls of the stacked structure may then be forwarded into substrate
100
to form source
110
and drain
112
. An oxide layer
114
may be thermally grown upon the perimeter of the stacked structure and upon exposed regions of substrate
100
that overlie source
110
and drain
112
. Due to exposure to thermal energy during this process, impurities implanted in source and drain regions
110
and
112
undergo lateral migration toward the channel region underneath tunneling oxide
102
, resulting in the configuration depicted in FIG.
1
.
In subsequent processing, control gate
108
will be coupled to a word line conductor. Bit line conductors can be formed within contact windows of oxide layer
114
for electrical connection to drain region
112
. In one approach, floating gate
104
can be programmed by grounding source
110
and drain
112
and applying a relatively high voltage to control gate
108
. During programming, electrons from the device substrate pass through tunneling oxide
102
into floating gate
104
by a tunneling mechanism known as Fowler-Nordheim tunneling. Those acquainted with semiconductor device physics understand Fowler-Nordheim tunneling as an instantiation of the quantum mechanical prediction that an electron will pass from the conduction band of one silicon region to that of another silicon region through an intervening silicon dioxide barrier, notwithstanding that such a travel is forbidden by notions of classical physics. See R. H. Fowler and L. Nordheim, “Electron Emission in Intense Electric Fields,”
Proc. Roy.Soc. London
, A119, 173 (1928).
As electrons accumulate in floating gate
104
, the accelerating electric field diminishes and the flow of electrons to floating gate
104
decreases. Programming of the memory cell is performed for a time that is sufficient to store a desired level of charge in the floating gate. Discharge of floating gate
104
to erase the cell can be achieved by grounding control gate
108
, substrate
100
, and source region
110
and applying a relatively high voltage to drain region
112
.
Specifically, in order to program (write date to) the exemplary Floating-Gate cell depicted in
FIG. 1
, a voltage equal to approximately 20 volts (V) is applied to the control gate of the FET, while the drain is grounded. Current flows from the drain and through the channel so that electrons are injected through the oxide layer into the floating gate. As indicated above, electron injection occurs in this manner in accordance with Fowler-Nordheim tunneling effect. Injected electrons accumulate in the floating gate, causing the V
T
of the FET to increase and the intensity of the electric field between the gate and drain of the FET to increase.
In order to erase data previously written to the Floating-Gate EEPROM, the FET source, drain and substrate are grounded. A reverse bias of 20V is supplied to the control gate. Electrons that had accumulated in the floating gate during the immediately preceding programming operation flow to the substrate through the tunnel oxide layer
102
, again in accordance with Fowler-Nordheim effects. As electrons vacate the floating gate, the FET V
T
decreases, as does the intensity of the electric field between the drain and the control gate.
The Floating-

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