Split gate non-volatile memory cell with improved endurance...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257SE29300, C257SE29112, C257SE21422, C257SE21179, C438S266000, C438S260000

Reexamination Certificate

active

07923769

ABSTRACT:
A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

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U.S. Appl. No. 12/103,451, filed Apr. 15, 2008, Inventor Sung-Taeg Kang, et al.
Non-final-office action dated Apr. 6, 2010 in U.S. Appl. No. 12/103,246.

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