Split-gate non-volatile memory

Details Split-gate non-volatile memory Split-gate non-volatile memory

2003-08-11

2009-10-27

Warren, Matthew E (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S320000, C257S324000, C257SE29309

Reexamination Certificate

active

07608882

ABSTRACT:
A split-gate non-volatile memory cell is described, including a substrate, a charge-trapping layer on the substrate, a split gate on the charge-trapping layer, and a source/drain in the substrate beside the split gate. The split gate includes at least one split region directly over the charge-trapping layer, and the charge-trapping layer around the split region serves as a coding region. A NAND non-volatile memory array is also described including the above-mentioned split-gate non-volatile memory cells that are arranged in a NAND-type configuration.

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