Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2011-04-19
2011-04-19
Tran, Minh-Loan T (Department: 2826)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C257S320000, C257SE29129
Reexamination Certificate
active
07927994
ABSTRACT:
An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.
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Hu Yaw Wen
Jia James Yingbo
Kotov Alexander
Levi Amitay
Liu Xian
DLA Piper (LLP) US
Sengdara Vongsavanh
Silicon Storage Technology, Inc.
Tran Minh-Loan T
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