Split gate multi-bit memory cell

Details Split gate multi-bit memory cell Split gate multi-bit memory cell

2007-12-25

2007-12-25

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S317000, C257S318000, C257S319000, C257S320000, C257S321000

Reexamination Certificate

active

11101783

ABSTRACT:
A multi-bit memory cell (200) with a control gate (220) for controlling a middle portion of a channel region (208) provides improved operation including faster programming at smaller voltages and currents. The memory cell (200) includes a source (204) and a drain (206) diffused into a substrate (202) forming a channel region (208) therebetween. A first charge storing layer (214), a second charge storing layer (216) and the control gate (220) are formed on the substrate (202) over the channel region (208) and a gate (218) is formed over the source (204), the drain (206), the first and second charge storing layers (214, 216) and the control gate (220). Dielectric material (210, 212, 224, 226, 228) separates the source (204) and the drain (206) from the gate (218), and the control gate (220) from the first charge storing layer (214), the second charge storing layer (216) and the gate (218).

REFERENCES:
patent: 6215702 (2001-04-01), Derhacobian et al.
patent: 6721205 (2004-04-01), Kobayashi et al.
patent: 2002/0097621 (2002-07-01), Fujiwara
patent: 2003/0142550 (2003-07-01), Kawahara et al.
patent: 2004/0021171 (2004-02-01), Nishizaka
patent: 10144700 (2002-04-01), None
patent: 1300888 (2003-04-01), None
patent: WO 01/17031 (2001-03-01), None
patent: US06/12492 (2006-07-01), None

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