Split-gate memory device and method for accessing the same

Details Split-gate memory device and method for accessing the same Split-gate memory device and method for accessing the same

1997-06-16

1999-10-19

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257319, 257321, 36518518, H01L 29788

Patent

active

059693835

ABSTRACT:
An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).

REFERENCES:
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patent: 5614747 (1997-03-01), Ahn et al.
patent: 5691937 (1997-11-01), Ohta
patent: 5703388 (1997-12-01), Wang et al.
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patent: 5780891 (1998-07-01), Kauffman et al.
patent: 5796139 (1998-08-01), Fukase
Masanori Kikuchi et al., "Ti Silicidation Technology For High Speed EPROM Devices", IEEE Electron Dev.Soc., 1983 VLSI Symp., Sept. 13-15, 1983, pp. 112-113.

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