Split-gate memory cells and fabrication methods thereof

Details Split-gate memory cells and fabrication methods thereof Split-gate memory cells and fabrication methods thereof

2007-04-17

2010-02-23

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29300, C438S257000

Reexamination Certificate

active

07667261

ABSTRACT:
Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

REFERENCES:
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patent: 6337244 (2002-01-01), Prall et al.
patent: 6525959 (2003-02-01), Fastow
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patent: 6743675 (2004-06-01), Ding
patent: 6815760 (2004-11-01), Leung et al.
patent: 7202130 (2007-04-01), Liu et al.

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