Split gate memory cell in a FinFET

Details Split gate memory cell in a FinFET Split gate memory cell in a FinFET

2006-01-27

2009-06-09

Smith, Bradley K (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S619000, C257S314000, C257SE29264

Reexamination Certificate

active

07544980

ABSTRACT:
A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.

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PCT International Search Report and Written Opinion regarding International Application No. PCT/US 06/62281, Applicant's file reference SC14944TP, mailed Feb. 14, 2008.

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