Split gate memory cell

Details Split gate memory cell Split gate memory cell

1999-12-14

2001-11-06

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S320000, C257S321000

Reexamination Certificate

active

06313500

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory cell and more particularly a split gate memory cell useful for low voltage operation.
2. Description of the Prior Art
As device technology scales down, doping concentrations in devices keep increasing. The resultant decrease in oxide/junction breakdown voltage makes it difficult to utilize high voltages required for the operation of non-volatile (NV) memory cells. Further, in the select gate of a split-gate memory cell itself, one needs relatively thicker gate oxides to prevent oxide breakdown. This makes it difficult to scale the V
t
's of the select gate device and thus leads to poorer low voltage operation.
Scientists at Samsung Corp. have proposed the idea of a built-in charge pump for use in stacked gate cells (termed Boosted wordline cell) in an effort to address the aforementioned problems. The cells proposed by Samsung require the use of a triple poly structure. The present invention addresses the aforementioned problems through the use of a novel cell have a two-poly structure.
SUMMARY OF THE INVENTION
The present invention comprises a novel split gate memory cell and its method of operation.
The novel split gate cell comprises a silicon substrate having a tunnel oxide layer on a portion of its surface and a first control gate and a floating gate electrode spaced from each other and preferably formed from the same material over the tunnel oxide. A dielectric layer overlies the first control gate and the floating gate electrodes, including the surface of the electrodes in the area between them. A second control gate, which is physically separated from the first control gate is provide over the dielectric layer and in the space between the first control gate and the floating gate. A highly doped region may be provided in the silicon substrate in the region under the separation of the first control gate and the floating gate. Source and drain regions are also provided in the substrate with optional halo-implants adjacent thereto.
The novel memory cell is fabricated by providing a tunnel oxide layer on the surface of a silicon substrate; forming a conductive layer over the tunnel oxide; forming a space in the conductive layer so as to provide a control gate and a floating gate electrode separated from each other but made from the same deposited or grown layer; forming a highly doped region in the substrate below the space between the aforementioned electrodes; forming a dielectric layer over the surfaces of the aforementioned electrodes; and forming a second control gate over the dielectric layer.
In operation, the novel device can operate at lower voltages than conventional split gate memory cells. The device is programmed by first applying a voltage to the second control gate, electrically floating the node second control gate and the applying a voltage to the first control gate. Due to a coupling between control gates, the voltage on the second control gate is automatically increased upon application of a voltage to the first control gate. The drain may then be pulsed to initiate hot carrier injection into the floating gate or a small charge pump may be provided to generate higher voltages. In the erase mode, erasure can be accomplished with the first control gate open and and the second control gate held at a negative voltage with a positive drain voltage. Alternatively, one can erase utilizing a low voltage charge pump from the coupling between the control gates but using a negative voltage. Further, erase can be accomplished by a channel erase process. During the Read operation, both of the control gates are brought to the wordline voltage.


REFERENCES:
patent: 5278439 (1994-01-01), Ma et al.
patent: 5877523 (1999-03-01), Liang et al.
patent: 6087695 (2000-07-01), Chen
patent: 6093945 (2000-07-01), Yang
patent: 6103573 (2000-08-01), Harari et al.
patent: 6204530 (2001-03-01), Choi
patent: 6215688 (2001-04-01), Pio
H. Wong, Gate Current Injection is MOSFET's with a Split-Gate (Virtual Drain) Structure, IEEE Electron Device Letters, vol. 14, No. 5, pp. 262-264, May 1993.*
S. Ogura et al., Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash, IEEE/IEDM, pp. 987-990, 1998.

Affiliated with

Also associated with

Rating

Split gate memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Split gate memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Split gate memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2570851