Split gate flash memory with buried source to shrink cell dimens

Details Split gate flash memory with buried source to shrink cell dimens Split gate flash memory with buried source to shrink cell dimens

1999-11-15

2000-09-26

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257317, 438257, H01L 29788

Patent

active

061246093

ABSTRACT:
A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.

REFERENCES:
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5350937 (1994-09-01), Yamazaki et al.
patent: 5385856 (1995-01-01), Hong
patent: 5527727 (1996-06-01), Kim
patent: 5627393 (1997-05-01), Hsu
patent: 5780341 (1998-07-01), Ogura
patent: 6037221 (1998-07-01), Lee et al.

Affiliated with

Also associated with

Rating

Split gate flash memory with buried source to shrink cell dimens does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Split gate flash memory with buried source to shrink cell dimens, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Split gate flash memory with buried source to shrink cell dimens will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2102259