Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-31
2003-03-04
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C438S260000
Reexamination Certificate
active
06528844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to split-gate FLASH memory cells and, more particularly, to a split-gate FLASH memory cell with a tip in the middle of the floating gate.
2. Description of the Related Art
An electrically-erasable, programmable read-only-memory (EEPROM) cell is a semiconductor memory structure that stores one of two logic states even when power is removed from the structure. A conventional EEPROM cell is a two-transistor device that includes a select transistor and a floating-gate memory transistor.
A split-gate FLASH memory cell is a type of EEPROM cell that merges the select transistor and the floating-gate memory transistor into a single transistor. In a split-gate FLASH memory cell, a merged gate functions as both the gate of the select transistor and the control gate of the memory transistor.
FIG. 1A
shows a plan view that illustrates a prior-art, split-gate FLASH memory cell
100
.
FIG. 1B
shows a cross-sectional view taken along line
1
B—
1
B of FIG.
1
A. In the example shown in
FIGS. 1A and 1B
, memory cell
100
is formed in a p-substrate
110
that includes a pair of conventionally-formed, spaced-apart, shallow trench isolation regions STI.
Memory cell
100
includes spaced-apart n+ source and drain regions
112
and
114
that are formed in substrate
110
, and a channel region
116
that is defined between source and drain regions
112
and
114
. Channel region
116
, in turn, includes a first channel region
116
A, a second channel region
116
B, and a third channel region
116
C.
As further shown in
FIGS. 1A and 1B
, memory cell
100
includes a layer of gate oxide
120
that is formed on substrate
110
over channel region
116
, and a floating gate
122
that is formed on gate oxide layer
120
over first channel region
116
A. In addition, memory cell
100
also includes a layer of tunneling oxide
124
that is formed on gate oxide layer
120
over second channel region
116
B, the side walls of floating gate
122
, and the top surface of floating gate
122
.
Memory cell
100
further includes a merged gate
126
that is formed on gate oxide layer
120
over third channel region
116
C, and tunneling oxide layer
124
over floating gate
122
. The portion of merged gate
126
that is formed over third channel region
116
C functions like the gate of a select transistor of a conventional EEPROM cell. In addition, the portion of merged gate
126
that is formed over first channel region
116
A functions like the control gate of a floating-gate memory transistor of a conventional EEPROM cell.
In operation, after memory cell
100
has been erased, floating gate
122
is left with a first charge. When memory cell
100
is then read, ground is applied to substrate
110
and source
112
, a first positive voltage is applied to drain region
114
, and a second positive voltage is applied to merged gate
126
.
The first positive voltage sets up a drain-to-source electric field, while the second positive voltage sets up a merged gate-to-substrate electric field. The merged gate-to-substrate electric field in first channel region
116
A is defined by several factors. These factors include the voltage differential, the separation distance, the dielectric constants of the materials, and the first charge stored on floating gate
122
.
Under the influence of the merged gate-to-substrate electric field, electrons are attracted to and accumulate at the surface of channel region
116
. The accumulated electrons, in turn, allow electrons to flow from source region
112
to drain region
114
under the influence of the drain-to-source electric field. The electron flow is detected and read to be, for example, a logic high.
After memory cell
100
has been programmed, a second charge is placed on floating gate
122
. Memory cell
100
is programmed by injecting electrons into floating gate
122
. As a result, the second charge is more negative than the first charge. As above, when memory cell
100
is read, ground is applied to substrate
110
and source
112
, the first positive voltage is applied to drain region
114
, and the second positive voltage is applied to control gate
126
.
The first positive voltage sets up the same drain-to-source electric field. The second positive voltage, however, sets up a different merged gate-to-substrate electric field in first channel region
116
A. In this case, the electric field is much weaker due to the negative value of the second charge stored on floating gate
122
.
The weaker merged gate-to-substrate electric field, in turn, fails to attract enough electrons to the surface of first channel region
116
A to allow electrons to flow from source region
112
to drain region
114
. The lack of electron flow is detected and read to be, for example, a logic low.
Memory cell
100
is erased by applying a third positive voltage to merged gate
126
, and ground or a negative voltage to source region
112
. (The substrate and drain regions can be grounded or floated.) The floating gate
122
will also receive a part of third positive voltage in accordance with capacitive coupling of the floating gate to merged gate
126
, source
112
, and substrate
110
.
The potential difference between the floating gate
122
and merged gate
126
sets up an electric field which has a magnitude that is sufficient to cause electrons on floating gate
122
to tunnel through tunneling oxide layer
124
to merged gate
126
via the well known Fowler-Nordheim process. The magnitude of the merged gate-to-floating gate electric field across tunneling oxide layer
124
is greatest at the covered edge of floating gate
122
where a tip
130
is present.
One problem with memory cell
100
is that when a large number of cells are fabricated, such as when wafers of memory arrays are formed, it is difficult to precisely replicate the steps that are used to form tip
130
. In a conventional fabrication process, one side of a tip is formed by an anisotropic etch (which is difficult to align), while the other side is formed by the bird's beak portion of a local oxidation of silicon (LOCOS)-grown field oxide region (which is difficult to control).
The conventional process also leads to variations in the polysilicon grain structure, the radius of curvature of tip
130
, the angle of tip
130
, and the distance from tip
130
to the overlying tunneling oxide. As a result, tip
130
can vary significantly from lot-to-lot, thereby providing an undesirably wide performance range.
Thus, there is a need for a method of forming a split-gate memory cell that provides a more controllable approach to fabricating the memory cell and, therefore, a narrower performance range.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a split-gate memory cell that provides a more controllable approach to fabricating a tip on the floating gate of the memory cell. In accordance with the present invention, a memory cell, which is formed in a semiconductor material of a first conductivity type, includes spaced apart source and drain regions of a second conductivity type that are formed in the semiconductor material.
The memory cell also includes a channel region that is defined in the semiconductor material between the source and drain regions. The channel region includes a first channel region, a second channel region that adjoins the first channel region, and a third channel region that adjoins the second channel region.
The memory cell further includes a layer of first insulation material that is formed on the semiconductor material over the channel region, and a floating gate that is formed on the layer of first insulation material over the first channel region. The floating gate has side wall surfaces, a top surface, and a central tip that extends away from a central portion of the top surface of the floating gate.
The memory cell additionally includes a layer of second insulation material that is formed on the layer of first insulation material over the second channel region, the side wal
Hopper Peter J.
Mirgorodski Yuri
Booth Richard
National Semiconductor Corporation
Pickering Mark C.
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