Split gate flash memory cell structure and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S315000, C257S300000

Reexamination Certificate

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06924527

ABSTRACT:
A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5045488 (1991-09-01), Yeh
patent: 5202850 (1993-04-01), Jenq
patent: 5278087 (1994-01-01), Jenq
patent: 5572054 (1996-11-01), Wang
patent: 6359303 (2002-03-01), Kanamori

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