Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-04-24
2007-04-24
Andujar, Leonardo (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S239000, C257S261000, C257SE29300, C257SE21422, C438S201000, C365S185010, C365S185240
Reexamination Certificate
active
11163223
ABSTRACT:
A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.
REFERENCES:
patent: 5889304 (1999-03-01), Watanabe et al.
Article titled “Scaling of CMOS FinFETs towards 10 nm” jointly authored by Chen et al., IEEE, pp. 46-48, 2003.
Chang Ko-Hsing
Chung Wu-Tsung
Huang Tsung-Cheng
Andujar Leonardo
Jianq Chyun IP Office
Powerchip Semiconductor Corp.
Wilson Scott R.
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