Split-gate EPROM cell using polysilicon spacers

Details Split-gate EPROM cell using polysilicon spacers Split-gate EPROM cell using polysilicon spacers

1991-07-09

1992-05-19

Jackson, Jr., Jerome

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 239, 365185, H01L 2968, H01L 2978, G11C 1134

Patent

active

051152886

ABSTRACT:
The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit process technologies, misalignment problems associated with the prior art split-gate cells are eliminated.

REFERENCES:
patent: 4455568 (1984-06-01), Shiota
patent: 4639893 (1987-01-01), Eiten
patent: 4794565 (1988-12-01), Wu et al.
Ali et al, VLSI Cir. Conf. Tokyo, Japan 1989, "A New . . . EPROM".
Perlegos et al IEEE Int. Sol. State Cir. Conf. Digest 1980 pp. 142-143 "A 64K . . . Technology".

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