Patent
1991-08-30
1992-05-19
James, Andrew J.
357 2312, 357 41, 357 55, H01L 2910, H01L 2978, H01L 2906
Patent
active
051152878
ABSTRACT:
A step-cut insulated gate static induction transistor can accurately make a channel length and a gate length and is excellent as a high speed transistor but is greatly affected by a deviation in mask alignment in the manufacturing process. This invention utilizes the fact that a gate portion formed in a previous processes is used as a mask in a post portion to thereby self-adjustably form the post portion, thus eliminating the influence of the deviation in mask alignment. In addition, a construction has been invented in which a current flowing through a portion apart from a gate between a drain and a source can be restricted. The aforesaid manufacturing method is also used for this improved construction.
REFERENCES:
patent: Re29971 (1979-04-01), Nishizawa et al.
patent: 4427990 (1984-01-01), Nishizawa
Chang et al, "Vertical FET Random-Access Memories with Deep Trench Isolation", IBM Technical Disclosure Bulletin, vol. 22, No. 8B, Jan. 1980.
Nishizawa Jun-ichi
Suzuki Sohbe
Takeda Nobuo
James Andrew J.
Ngo Ngan Van
Research Development Corporation of Japan
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