Split delay transmission line

Details Split delay transmission line Split delay transmission line

2001-03-29

2004-03-23

Vo, Tim (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S305000, C361S760000, C361S803000, C326S030000

Reexamination Certificate

active

06711640

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to motherboard interconnects.
BACKGROUND OF THE INVENTION
FIG. 1
represents a computer system that includes a typical DRAM bus far end cluster. System
100
includes memory controller
101
that is coupled to far end cluster
102
at “T” junction
103
by relatively long trace
104
. Far end cluster
102
includes several closely spaced DRAMs
105
. DRAMs
105
are separated into first set
106
and second set
107
at junction
103
. First signal line
108
passes from junction
103
to last DRAM
109
included in first set
106
and second signal line
110
passes from junction
103
to last DRAM
111
included in second set
107
.
Impedance mismatch between trace
104
and the combination of signal lines
108
,
110
may result in poor signal integrity for signals that DRAMs
105
receive.
FIG. 2
represents a signal waveform that may result when driving a signal into a low impedance far end cluster—like the one illustrated in FIG.
1
. Because of the impedance mismatch, signal reflections, which occur when a signal reaches the cluster, produce ledges
201
. The load that DRAMs
105
present on signal lines
108
,
110
, can cause those ledges, e.g., ledge
202
, to have slope reversal (i.e., regions where a rising edge experiences a short voltage drop or where a falling edge experiences a short voltage rise).
To prevent such ledges from occurring at the DRAM receiver's switching threshold, stable system design may require all timings to be taken after the ledges. For example, if a ledge with slope reversal occurs on a signal's rising edge, it may be necessary to delay the latching of data to ensure that the receiver properly detects a voltage that exceeds the switching threshold. Adding delay to ensure that the receiver switches state as intended may reduce the maximum speed at which signals are driven between memory controller
101
and DRAMs
105
. Even when adding this delay, unless there is sufficient noise margin, such ledges might still cause a false trigger to occur, when data is to be latched into a DRAM, if they cause the slew rate to be insufficient to change the state of the input receiver at that time.
For example, lines
203
and
204
may designate the input voltage levels required for the receiver to switch—line
203
designating the input high voltage (“Vih”) and line
204
designating the input low voltage (“Vil”). When a rising edge passes through Vih, the DRAM receiver will switch from a first state to a second state (e.g., a low state to a high state.) Likewise, when a falling edge passes through Vil, the DRAM receiver will switch from a first state to a second state. The DRAM receiver will properly switch state as long as the voltage exceeds the switching threshold (for a rising edge), or falls below the switching threshold (for a falling edge), when the receiver latches data. As long as ledges
201
occur outside of the switching region, they should not prevent the correct latching of data into the receiver. As a result of system noise, however, receiver thresholds could change dynamically causing ledges, including ledges with slope reversal, to develop within the switching region—even when the system was designed to prevent that effect. If that occurs, incorrect data might be latched into the receiver.
Accordingly, there is a need for an improved motherboard interconnect that prevents formation of ledges with slope reversal as a signal rises and falls. There is a need for such a motherboard interconnect that enables DRAM receivers to latch data at a relatively high frequency without risk that such ledges will develop, which cause the receiver to accept incorrect data. The present invention provides such a motherboard interconnect.


REFERENCES:
patent: 6067594 (2000-05-01), Perino et al.
patent: 6381164 (2002-04-01), Fan et al.
patent: 6438012 (2002-08-01), Osaka et al.
patent: 6578125 (2003-06-01), Toba

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