Split-Control gate electrically erasable programmable read only

Details Split-Control gate electrically erasable programmable read only Split-Control gate electrically erasable programmable read only

1997-04-07

1999-03-30

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257299, 257315, 257321, H01L 29788

Patent

active

058893032

ABSTRACT:
An EEPROM cell (32) is formed having a vertical select gate (34) and a horizontal select gate (40). The vertical select gate (34) and the horizontal select gate (40) enable two dimensional decoding which selects which one or which plurality of memory cells (32) are enabled for program, erase and read operations. An additional select gate having a control electrode (44) can be added to the cell (32) to provide additional decoding as is necessary. This split gate EEPROM cell (32) can be readily integrated onto an integrated circuit which also contains flash memory (204). The flash memory (204) and the split control gate EEPROM array (202) can share the same common charge pumps circuit (208).

REFERENCES:
patent: 4274012 (1981-06-01), Simko
patent: 4630087 (1986-12-01), Momodomi
patent: 5304503 (1994-04-01), Yoon et al.
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patent: 5512505 (1996-04-01), Yuan et al.
patent: 5612913 (1997-03-01), Cappelletti et al.
patent: 5668757 (1997-09-01), Jeng
Tadashi Shibata et al., "An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", IEDM 1991, pp. 919-922.

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