Split computer architecture

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S305000, C710S314000, C710S300000

Reexamination Certificate

active

07020732

ABSTRACT:
A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

REFERENCES:
patent: 3925762 (1975-12-01), Heitlinger et al.
patent: 4384327 (1983-05-01), Conway et al.
patent: 4764769 (1988-08-01), Hayworth et al.
patent: 4959833 (1990-09-01), Mercola et al.
patent: 5235595 (1993-08-01), O'Dowd
patent: 5430848 (1995-07-01), Waggener
patent: 5566339 (1996-10-01), Perholtz et al.
patent: 5659707 (1997-08-01), Wang et al.
patent: 5664223 (1997-09-01), Bender et al.
patent: 5732212 (1998-03-01), Perholtz et al.
patent: 5754836 (1998-05-01), Rehl
patent: 5764479 (1998-06-01), Crump et al.
patent: 5764924 (1998-06-01), Hong
patent: 5764966 (1998-06-01), Mote, Jr.
patent: 5781747 (1998-07-01), Smith et al.
patent: 5799207 (1998-08-01), Wang et al.
patent: 5812534 (1998-09-01), Davis et al.
patent: 5948092 (1999-09-01), Crump et al.
patent: 6003105 (1999-12-01), Vicard et al.
patent: 6012101 (2000-01-01), Heller et al.
patent: 6016316 (2000-01-01), Moura et al.
patent: 6065073 (2000-05-01), Booth
patent: 6070214 (2000-05-01), Ahern
patent: 6084638 (2000-07-01), Hare et al.
patent: 6134613 (2000-10-01), Stephenson et al.
patent: 6146158 (2000-11-01), Peratoner et al.
patent: 6202116 (2001-03-01), Hewitt
patent: 6240481 (2001-05-01), Suzuki
patent: 0 270 896 (1988-06-01), None
patent: 0 395 416 (1990-10-01), None
patent: 0 844 567 (1998-05-01), None
patent: 11-184800 (1999-07-01), None
patent: 11-184801 (1999-07-01), None
Hsieh, Cheng-Ta et al., “Architectural Power Optimization by Bus Splitting”, Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, pp. 612-616.
IBM Technical Disclosure Bulletin, “Proceedure and Design to Facilitate”, Apr. 1994, vol. 37, Issue 4B, pp. 215-216.
Schutti, Markus et al., “Data Transfer Between Asynchronous Clock Domains without Pain”, RIIC, SNUG Europe 2000, Rev. 1.1, Feb. 2000, pp. 1-12.
Hill, Tom, “Virtex Design Methodology using Leonardo Spectrum 1999.1”, Applications Note, Exemplar Logic Technical Marketing, Rev. 3.0, Apr. 1999, pp. 1-47.
Duft, Ann et al. (ed.), “Xilinx Breaks One Million-Gate Barrier with Delivery of New Virtex Series”, Press Kit, Xilinx, Oct. 1998.
Mobility Electronics, Inc. Brochure for PCI Split Bridge, Scottsdale, AZ, © 1999.
“Digital Semiconductor 21152 PCI-TO-PCI Bridge, Data Sheet”, Feb. 1996, Digital Equipment Corporation, Maynard, Mass.
“PCI Local Bus Specification, Revision 2.1”, Jun. 1995, The PCI Special Interest Group, Portland, Oregon.
International Search Report, PCT/US99/25291 mailed Feb. 7, 2000.
International Search Report, PCT/US99/25290 mailed Feb. 10, 2000.

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