Split charge storage node inner spacer process

Details Split charge storage node inner spacer process Split charge storage node inner spacer process

2007-10-17

2010-11-09

Le, Thao X (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21179, C257SE21422, C257SE21680, C438S361000

Reexamination Certificate

active

07829936

ABSTRACT:
Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

REFERENCES:
patent: 2005/0255651 (2005-11-01), Qian et al.
patent: 2007/0161191 (2007-07-01), Yuan et al.
patent: 2008/0303067 (2008-12-01), Rao et al.

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