Spin transistor using double carrier supply layer structure

Details Spin transistor using double carrier supply layer structure Spin transistor using double carrier supply layer structure

2008-12-23

2011-11-15

Dickey, Thomas L (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE43003

Reexamination Certificate

active

08058676

ABSTRACT:
A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.

REFERENCES:
patent: 5767539 (1998-06-01), Onda
patent: 2007/0059877 (2007-03-01), Koo et al.
Supriyo Datta and Biswajit Das, “Electronic analog of the electro-optic modulator”, Feb. 12, 1990, 3 Pages.

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